• 한국실내디자인학회논문집
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• 제26권6호
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• pp.42-52
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• 2017

In this modern world of drastic change, folding architecture was an alternative that offered a novel architectural insight. Today, the folding technique is being used above and beyond architecture, spreading to fashion, lighting, medicine, etc. Especially in the interior space design field, the folding technique is in the limelight as an alternative to create an original space for modern society. However, research and experiments into folding mainly remains at philosophical interpretation or architectural examples, and even these were mostly before the 2000s. Therefore, the present study determined it necessary to look deeply into the post-2000s folding technique focusing on interior space. In this paper, 33 cases of indoor space where folding technique appears are derived, and classified them again by use. The folding technique which was the first step of Sophia Vyzoviti's experiment on her book, "Folding Architecture" was extracted and used as the framework. We summarizes the range of application of folding techniques (interior space in general, floor, wall, ceiling, etc.) and major folding techniques by combining photographs, drawings, and descriptions of the works of the architects. This paper summarizes the characteristics of the space described comprehensively, and draws out the spatial characteristics of the modern interior space where the folding technique appears.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• 복식문화연구
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• 제30권4호
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• pp.513-528
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• 2022

The purpose of this study is to understand the concept of zero-waste design and to apply Sophia Vyzoviti's folding techniques to develop a zero-waste fashion design method that contributes to sustainable fashion design. In this study, we explore the method and characteristics of zero-waste fashion design based on the concept of folding described in Sophia Vyzoviti's book on folding techniques. Using the autonomy of Sophia Vyzoviti's folding technique, four changeable folding fashion designs were developed and produced, demonstrating zero-waste fashion design. The results were as follows. First, the development of fashion designs using Sophia Vyzoviti's folding techniques enabled the development and production of free and creative zero-waste fashion designs that were three-dimensional, continuous, fluid, and full of potential. Second, the production of zero-waste patterns was further developed into a transformable fashion design that can be used with geometric patterns. These folding techniques produced a fashion design method that could transform one piece of clothing, demonstration the potential for maintenance of creativity using a zero-waste design based on these folding techniques. Third, the double-faced fabric, Neoprene, was chosen as an appropriate material as it emphasizes the depth of folding with application of two colors and its cotton/polyester blend that is suitable for folding.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.376-382
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• 2014

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

• 대한전자공학회논문지SD
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• 제45권11호
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• pp.13-20
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• 2008

본 논문에서는 1.8YV 12-bit 10MSPS CMOS A/D 변환기 (ADC)를 제안한다. 제안하는 ADC 는 12-bit의 고해상도를 구현하기 위해 even folding 기법을 이용한 Folding/Interpolation 구조로 설계하였다. ADC의 전체 구조는 2단으로 구성된 Folding/Interpolation 구조로써, 각각의 folding rate (FR)은 8을 적용하였고, interpolation rate (IR)은 $1^{st}$ stage 에서 8, $2^{nd}$ stage 에서 16을 적용하여 설계함으로써 고해상도를 만족시키기 위한 최적의 구조를 제안하였다. 또한 SNR 을 향상시키기 위하여 Folding/Interpolation 구조 자체를 cascaded 형태로 설계하였으며, distributed track and hold를 사용하였다. 제안하는 ADC는 $0.18{\mu}m$ 1-poly 4-metal n-well CMOS 공정을 사용하여 제작되었다. 시제품 ADC 는 측정결과 10MSPS 의 변환속도에서 약 46dB의 SNDR 성능특성을 보이며, 유효 칩 면적은 $2000{\mu}m{\times}1100{\mu}m$의 면적을 갖는다.

• 전자공학회논문지
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• 제50권1호
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• pp.137-147
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• 2013

본 논문에서는 폴딩 구조에 저항열 인터폴레이션 기법을 적용한 1.2V 8b 1GS/s CMOS folding-interpolation A/D 변환기(ADC)에 대해 논한다. 기존 폴딩 ADC가 갖는 경계조건 비대칭 오차를 최소화하기 위해 홀수개의 폴딩 블록과 프랙셔널 폴딩 비율(fractional folding rate)을 사용하는 구조를 제안한다. 또한, 프랙셔널 폴딩기법을 구현하기 위해 덧셈기를 사용하는 새로운 디지털 인코딩기법도 제안한다. 그리고 iterating offset self-calibration 기법과 디지털 오차 보정 회로를 적용하여 소자 부정합과 외부 요인에 의한 노이즈 발생을 최소화하였다. 제안하는 A/D 변환기는 1.2V 0.13um 1-poly 6-metal CMOS 공정을 사용하여 설계 되었으며 $2.1mm^2$ 유효 칩 면적과(A/D 변환기 core : $1.4mm^2$, calibration engine : $0.7mm^2$), 350mW의 전력 소모를 나타내었다. 측정결과 변환속도 1GS/s에서 SNDR 46.22dB의 특성을 나타내었다. INL 과 DNL 은 자체보정회로를 통해 모두 1LSB 이내로 측정되었다.

• 펄프종이기술
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• 제47권4호
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• pp.168-176
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• 2015

The history of paper folding had continued before that the paper manufacturing technique was spread in the 3rd century and it was used for witchcrafts and rituals. Fold means as was used with the word Cheop and Jeopji. In the Three Kingdoms period, the conical hat with fabric spread as customs, then it was made of the paper that led the popularization of paper folding form the early Joseon Dynasty. Paper crafts and living things with paper are mostly derived from fabrics except the paper written for saint's name related God. In the period of the tribe nation, witchcrafts and rituals brought to Japan via the Korean Peninsula, as a result Kami which means God in Japanese that becomes the paper. The first folding fan was made to develop from the fan, Baekseopsun in the end of Goryeo Dynasty. It was an outstanding application of paper folding crafts. Since the early Joseon Dynasty, paper flower folding has considered as the virtue of savings and has developed one of the Korean traditional paper arts. Paper folding has also developed in the practical uses like the other Korean paper arts but paper folding that was developed as seasonal customs, playing or religious purpose showed a different trend from Korean paper arts.

• ETRI Journal
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• 제29권3호
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• pp.408-410
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• 2007

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ${\pm}0.6$ LSB and ${\pm}1.6$ LSB, respectively.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집C
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• pp.100-105
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• 2001

The manufacturing of metal bellows consists of the four main forming processes, deep-drawing, ironing, tube bulging and folding. Among these, the bulging and folding processes are critically important because the quality of metal bellows is greatly influenced by the forming conditions of these processes. In the present study, the finite element analysis technique is applied to the bulging and folding processes to obtain information about the design parameters of a metal bellows.

• 대한전자공학회논문지
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• 제23권5호
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• pp.674-680
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• 1986

In this paper, a new design method for high density PLA by a simple row folding technique is proposed. The normal input line and its complement line of different two input lines are folded on the same row. Especially the only one input line pair of the different two input lines are folded by this method. Conseqently, the results of folding are better than those of conventional methods. An efficient technique of ordering columns is described. Also, constraints about outside circuitry are consideted in this algorithm. The proposed algorithm has been implemented on a personal computer by C language.