• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.1
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• pp.95-103
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• 2009

We improve the performance of WCDMA repeater by cancelling the feedback interference radio signal under the fixed point implementation. Floating-point DSP or FPGA to implement the ICS algorithm may have an disadvantage of high cost, To solve this problem, we suggest the ICS algorithm based on LMS under fixed point operation, and show the validity of our results by comparing with the floating-point results through numerical simulation.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1776-1781
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• 2008

To reduce interior noise of running vehicles, a floating floor construction has been widely used in recent railway industry. Among the key factors of the floating floor design, dynamic stiffness is of most important in acoustical point of view. Sometimes hard rubber type supports have often been selected due to the other design constraints such as heavy load condition, durability of rubber element and its cost etc., even though it seems like the softer support, the better isolation of noise and vibration. In this paper two representative floor supports have been considered to evaluate their effectiveness in interior noise contribution: one is a soft rubber and another is a relatively hard one. From the measured dynamic stiffness of the specimens, equivalent stiffness of actual floating floor has been derived to use in the analytical models. Calculated air-borne and structure-borne noise insulation properties of the floating floors have been compared with experiments in prototype car. In full car model interior noise levels of running vehicles have been predicted to quantify the effectiveness of the two different floating support materials and verified through the measured inside noise levels of actual train as well. By comparison with difference of running noise levels two materials for floor support can be investigated quantitatively so that it could be applied in floating floor design.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2072-2075
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• 2003

This paper is studied the high speed processing moving picture encodec to compress and encode a moving picture by real time. This is used the new motion vector search algorithm with smallest search point in H.263 encodec, and is applied the integer DCT for the encodec by converting a moving picture. The integer DCT behaves DCT by the addition operation of the integer using WHT and a integer lifting than conventional DCT that needs the multiplication operation of a floating point number. Therefore, the integer DCT can reduce the operation amount than basis DCT with having an equal PSNR because the multiplication operation of a floating point number does not need.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.1
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• pp.22-25
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• 1979

The mechanical floating-mass which is analogous to an electrical floating- capacitance may not come across because a mass element in a mechanical network must be attracted to rho ground which is the reference point. In this study the mechanical floating-mass is fonstructed by employing two simple support levers, one link, one mass, and four frictionless hearings. It also shows that the mechanical device can be used to give various equivalent masses by altering the arm ratio of the levers.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.259-259
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• 2000

In the recent, the size of hardware is smaller and the structure is simpler, without reducing the performance of the digital controller. Accordingly, the fixed-point arithmetic is very important in the digital controller. This paper presents simulation to apply the robust control algorithms to DVDR servo controller using the floating-point and fixed-point arithmetic from the matlab. Also, it analyses and compares the performance of control algorithms in the each of point calculation and presents a method for improvement of drop in the performance, quantization error and overflow/underflow from using the fixed-point arithmetic

• Journal of Ocean Engineering and Technology
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• v.26 no.4
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• pp.77-85
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• 2012

A study was performed on the design of a mooring line to maintain the position of a floating WEC (wave energy conversion) system. The procedure to design a mooring line is set up and the safety of the designed mooring system is evaluated using commercial software, Orcaflex. The characteristics curve for one line is analyzed to determine the properties and pretension of a mooring line. While considering the ocean environmental condition and importance of a floating WEC system, a multi-line layout is determined. A 4-point mooring system with 4 lines shows the instability in the yaw motion of the floating WEC system under a designed ocean environmental condition. The redesigned 4-point mooring system with 8 lines is found to be safe on the condition of a harsh ocean environment. The floating WEC system with the redesigned mooring system also shows stable motion in surge and pitch under operating conditions. From a parametric study on the mooring line length, the extreme value of the mooring line tension is found to be very sensitive to the pretension and length of mooring line. The results of this study can contribute to the establishment of a design procedure for mooring lines.

• The Mathematical Education
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• v.21 no.3
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• pp.23-24
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• 1983