• Journal of Practical Engineering Education
• /
• v.13 no.2
• /
• pp.221-232
• /
• 2021

The purpose of this study is to explore the design direction of artificial intelligence convergence liberal arts subjects based on flip learning and maker education through analysis of learner needs in a non-face-to-face classroom environment caused by COVID-19. To this end, we analyzed the priorities of subject content elements by using the Borich needs assessment and The Locus for Focus model along with students' perceptions of flip learning for students who took and did not take maker education-based liberal arts courses. Based on this, it was used as basic data for designing the curriculum. The study results are as follows. First, the content elements of the artificial intelligence liberal arts curriculum based on maker education consisted of a total of 9 areas and were designed as a class using flip learning. Second, the areas with the highest demand for education are 'Artificial Intelligence Theory', 'Artificial Intelligence Programming Practice', 'Physical Computing Theory', 'Physical Computing Practice', followed by 'Convergence Project', '3D Printing Theory', '3D Printing practice' was decided. Third, most of the questionnaires regarding the application of flip learning in maker education-based artificial intelligence liberal arts subjects showed positive responses regardless of whether they took the course, and the satisfaction of the students was very high. Based on this, an artificial intelligence-based convergence liberal arts curriculum using flip learning and maker education was designed. This is meaningful in that it provides an opportunity to cultivate artificial intelligence literacy for college students by preparing the foundation for artificial intelligence convergence education in liberal arts education by reflecting the needs of students.

• Journal of Welding and Joining
• /
• v.24 no.2
• /
• pp.64-70
• /
• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.4
• /
• pp.53-58
• /
• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.10
• /
• pp.3226-3235
• /
• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Journal of radiological science and technology
• /
• v.32 no.1
• /
• pp.101-106
• /
• 2009

Purpose of this study is to compare the signal intensity (SI) and CNR with T1 weighted image using FLASH at 3T abdominal MRI by varying flip angle (FA). Totally 20 patients (male : 12, female : 8, Age : $28{\sim}63$ years with mean : 51) were examined by 3 Tesla MR scanner (Magnetom Tim Trio, SIEMENS, Germany) with 8 channel body array coil between september and October 2008. Imaging parameters were as follows : FLASH sequence, TR : 120 ms, TE : minimum, FOV (field of view) : $360{\times}300\;mm$, Matrix : $256{\times}224$, slice : 6 mm, scan time : 15 sec and Breath-hold technique. Abdominal image, with a 50 ml syringe filled with water placed in the FOV measuring the water signal, were acquired with varying FA through $10^{\circ}$ to $90^{\circ}$ with $10^{\circ}$ interval. SI's were measured three times at liver parenchyme, water, spleen and background and averaged. The CNR's were measured between the ROIs (region of interest). Statistic analysis was performed with ANOVA test using SPSS software (version 17.0). Less than FA $30^{\circ}$, abdominal images were severely inhomogeneity. Especially, T1 effect of water signal was weak. As the flip angle increased, the signal intensity decreased at all the regions. Especially, flip angle of the highest signal intensity was observed with $40^{\circ}$ at the liver parenchyme, $20^{\circ}$ at water, $30^{\circ}$ at the spleen, respectively. The CNR between liver and water was -60.92 at FA $10^{\circ}$ and 15.16 at FA $80^{\circ}$. The CNR between liver and spleen was -3.18 at FA $10^{\circ}$ and 9.65 at $80^{\circ}$. In conclusion, FA $80^{\circ}$ is optimal for T1 weighted effect using FLASH pulse sequence at 3.0 T abdominal MRI.

• The Journal of the Convergence on Culture Technology
• /
• v.7 no.4
• /
• pp.211-225
• /
• 2021

The purpose of this study was to investigate the effect of academic self-efficacy, task value, behavioral participation, cognitive participation, emotional participation, and initiative participation on learning satisfaction in 462 college students who took a flip learning class. Results, As for the direct effect of variables affecting learning satisfaction, behavioral participation was the largest factor, followed by initiative participation, task value, emotional participation, and academic self-efficacy. These variables explained 86% of learning satisfaction. Academic self-efficacy and task value had an indirect effect on learning satisfaction through behavioral, emotional, and proactive participation. In the multi-group moderating effect with the upper-middle class (B+ or higher) and the lower-middle class (below B) group as the moderating variables, there was a partial moderating effect because the path coefficients of leading participation and learning satisfaction differed between the groups. It is necessary to seek various ways to increase the degree of participation in learning and to develop an intervention strategy through a program tailored to each individual.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.10
• /
• pp.889-895
• /
• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• IEIE Transactions on Smart Processing and Computing
• /
• v.6 no.3
• /
• pp.220-227
• /
• 2017

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

• Journal of Institute of Control, Robotics and Systems
• /
• v.20 no.10
• /
• pp.1067-1072
• /
• 2014

The ability to overcome obstacles is necessary for field robots for various applications including the ability to climb stairs. While much research has been performed focusing on overcoming obstacles, the resulting robots do not have sufficient ability to overcome obstacles such as stairs. In this research, the purpose is to overcome relatively large obstacles by flipping locomotion through the modification of the stair climbing robotic platform of the previous research. We propose two scenarios to overcome large obstacles: a rear wheel driving system and an elevation system using a ball screw. The research is performed based on static analyses on obstacle-climbing. As the simulation results indicate, we determined the optimal posture of the robot for climbing obstacles for rear wheel driving. Also, an elevation system is analyzed for obstacle climbing. Between the two scenarios an elevation system is determined to reduce the operating torque of the actuator, and the prototype was recently assembled. The climbing ability of the robotic platform is verified. We expect the application area for this robotic platform will be in accident areas of nuclear power plants.

• Journal of Korea Multimedia Society
• /
• v.25 no.5
• /
• pp.730-738
• /
• 2022

Based on visual Thinking theory, VR(virtual reality) game changes the traditional form of memory and maps the content into game elements to realize the immersive spatial memory mode. This paper analyzes the influencing factors of game design and system function construction. This paper proposes a hypothesis: with the help of visual thinking theory, VR game is helpful to improve learners' visual memory, and carries out research. The experiment sets different levels of game through empirical research and case analysis of memory flip game. For example, when judging two random cards. If the pictures are the same, it will be judged as the correct combination; if they are different, the two cards will be restored to the original state. The results are analyzed by descriptive statistical analysis and AMOS data analysis. The results show that game content using the concept of "Memory Palace", which can improve the accuracy of memory. We conclude that the use of spatial localization characteristics in flip games combining visual thinking can improve users' memory by helping users memorize and organize information in a Virtual environment, which means VR games have strong feasibility and effectiveness in improving memory.