• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.275-278
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• 1999

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.140-142
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• 2003

We have designed a SFQ (Single Flux Quantum) D2 Cell and Inverter(NOT) for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we have used Julia, XIC and Lmeter for simulations and layouts. We obtained the circuit margin of larger than $\pm$25%. After layout, we drew chip for fabrication of SFQ D2 Cell and Inverter. We connected D2 Cell and Inverter to jtl, DC/SFQ, SFQ/DC and RS flip-flop for measurement.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.4
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• pp.1-6
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• 1975

본 논문은 Platen동작제어에 의한 한글델레타이프외 세가지 제어논리회로를 설계검토하였다. 일반적인 논리회로 구성방법에 의한 설계결과, 상태, 상태변이함수 그리고 출력함수외 순서로 설계한 Pulse mode의 제어회로가 가장 간단하였다. 이때 필요한 기억소자는 D Flip-Flop 2회 뿐이었다.

• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.234-236
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• 1983

본 논문은 펄스형 순차회로(pulse mode sequential circuit)를 설계하는데 필요한 여러가지 복잡한 단계의 간소화를 목적으로 한, 컴퓨터를 이용한 회로 설계법을 제안하고자 한다. 여기서 제안된 방법에 의하면 여러 종류의 플립-플롭 (flip-flop)에 대한 회로의 설계를 반복 시행하고, 또 다출력 함수 최소화(multiple output function minimization) 방법을 적용함으로 해서 거의 적소에 가까운 비용으로 원하는 회로를 설계할 수 있다. 제안된 회로 설계법의 프로그램은 포트란(FORTRAN)으로 작성되었으며, 이에 의한 실에의 예와 그 결과를 종래 방법에 의한 것과 비교, 분석했다.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.68-74
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• 1985

In this Paper, we present a non-doglegging channel routing system for If layout using standard cells. This system produces a final two-layer wiring pattern in the horizontal track between two rows, each of which is a linear placement of standard cells of identical heights, satisfying the given net list specification. The layout of CMOS cell library Including nine primitive cells used in this paper is represented in CIF (Caltech Intermediate Form) using λ(Lambda) of 2 microns in Mead-Conway layout representation scheme. The cell dimension and 1/0 characteristics such as name, position and layer type of the pins are stored in Component Library to be used in the channel routing progranl, CROUT. 4 subprogram, NET-PLOT, was used to report a schemdtic layout result, and another subprogram, NETCIF was used to with a full-fledged final layout representation in GIF, A test run for realizing a dynamicmaster-slave D flip-flop with set/reset using primitive cells was shown to take 4 CPU seconds on VAX 11/780.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.

• Journal of IKEEE
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• v.19 no.3
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• pp.304-310
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• 2015

A SCALDO(Supercapacitor Assisted LDO) regulator is a new regulator having advantages of a SMPS(Switch Mode Power Supply) which has a good efficiency and a LDO(Low Drop-out) regulator which has stable output characteristics and good EMI(Electro Magnetic Interference) characteristics. However, a conventional SCALDO regulator needs a lot of power consumption to control its switches and it drops an efficiency of the circuit. In this paper, to reduce switching power consumption and improve an efficiency of the circuit, a new SCALDO regulator adopting MOSFETs as its switching parts is proposed and it is found out that the proposed SCALDO regulator has the maximum 9.5% higher efficiency than the conventional SCALDO regulator. We also try to simplify production process of the circuit by changing switching control method of the circuit from MCU(Micro-controller unit) based firmware control to hardware control using a comparator and a T-F/F(Flip Flop).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.600-603
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• 2008

In this paper, a new circuit design named memory-in-pixel for low power consumption of the liquid crystal display (LCD) is presented. Since each pixel has a memory, it is able to express 8 color grades using the data saved in the memory without the operation of the gate and source driver ICs so that it can reduce the power consumption of the LCD panel. A memory circuit consists of modified S-R flip-flop (NAND-type) implemented in the pixel, which can supply AC bias for operating the liquid crystal (LC) with the interlocking clocks (CLK_A and CLK_B). This circuit is more complex than the inverter-type memory circuit, but it has lower power consumption of approximately 50% than the circuit. We have investigated the power consumption both NAND and inverter-type memory circuit using a Smart SPICE for the resolution of $96{\times}128$. The estimated power consumption of the inverter-type memory was about 0.037mW. On the other hand, the NAND-type memory showed power consumption of about 0.007mW.