• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.1571-1572
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• 2015

본 논문에서는 GMM (Gaussian mixture model) 기반의 BS (background subtraction) 알고리즘을 이용한 이동 객체 검출기의 하드웨어 구조 설계 결과를 제시하였다. 설계된 이동객체 검출기는 1280 * 720 HD 해상도의 영상을 30 frames per second로 실시간 처리가 가능하다. 하드웨어 구현은 Verilog-HDL을 이용하였으며, FPGA 기반 구현 결과, 설계된 이동 객체 검출기는 582 Slice, 1,698 Slice LUT, 8 DSP48s, 1,769 Flip Flop, 691.2 KByte BRAM으로 구성되었음을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.396-397
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• 2015

본 논문에서는 이동 물체의 연속 위치 추적을 위한 무선 저전력 기저대역 모뎀을 설계 및 구현하였다. 설계된 모뎀은 단일 하드웨어로 16칩 및 32칩 대역확산을 통해 900MHz 대역 및 2.4GHz 대역을 동시에 지원하며, 250Kbps 이하 가변전송률 전송을 통해 다양한 통달거리 지원이 가능하다. FPGA 기반 구현 결과, 설계된 기저대역 모뎀은 8,010 Slice, 20,672 Slice LUT, 25,512 Flip Flop, 18Kb Block RAM으로 구성되었음을 확인하였다.

• Bulletin of the Korean Chemical Society
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• v.12 no.5
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• pp.525-529
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• 1991

A simple route is described for the selective functionalization of calixarene at the para positions of phenyl rings. Calix[4]arene tetraacetate 2, obtained from the treatment of calix[4]arene with acetic anhydride, undergoes Fries rearrangement to yield the diametrically para substituted p-diacetylcalix[4]arene 3 in 80% yield. The crystal and molecular strucutre has been determined by X-ray diffraction method. The crystals are orthorhombic, space group Pna21, with a = 11.121 (3), b = 10.374 (3), c = 21.690 (6) $\AA$ and Z = 4. The structure was solved by direct method and refined by full-matrix least-squares methods to final R of 0.036 for 1795 observed reflections. Each hydroxyl hydrogen atom is disordered over two positions. The macrocycle exists in the cone conformation which is determined by the strong circular intramolecular flip-flop type hydrogen bonds of phenolic OH, while crystal packing effects of the diametrically para-acetyl substituents seem to be responsible for the distortion of the cone conformation.

• Investigative Magnetic Resonance Imaging
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• v.23 no.3
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• pp.279-282
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• 2019

Neurosyphilis is an infection of the brain or spinal cord that is caused by the bacterium Treponema pallidum. Syphilitic myelitis, which involves the spinal cord, is a very rare form of neurosyphilis seen in patients with syphilis. It requires differentiation from other diseases of the spinal cord, including idiopathic transverse myelitis and spinal cord infarction. Herein, we describe the presentation and diagnosis of syphilitic myelitis in a 43-year-old woman, based on a flip-flop sign and candle guttering appearance depicted in magnetic resonance imaging and laboratory tests.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.254-259
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• 1987

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

• Journal of IKEEE
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• v.14 no.1
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• pp.1-7
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• 2010

This paper presents an implementation of the DisplayPort AUX(Auxiliary) Channel. DisplayPort uses Main link, AUX Channel and Hot Plug Detect line to transfer the video & audio data. For isochronous transport service, source device converts to image and audio data which are to be transported through the Main Link and transports the restructured image and audio data to sink device. The AUX Channel provides link service and device service for discovering, initializing and maintaining the Main link. Hot Plug Detect line is used to confirm the connection between source device and sink device. The AUX Channel is implemented with 3315 LUTs(Look Up Table), 1466 Flip Flops and 168.782MHz max speed synthesized using Xilinx ISE 9.2i at SoC Master3.

• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.557-565
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• 2020

In order for thermal degradationIn, excore nuclear flux monitoring system, as a monitoring and signal processing methodology of reactor power, monitors neutron pulses generated during nuclear fission as frequency status, and converts them into DC voltage, and then log values resultantly. The methods realy applied in the nuclear power plant are to construct combination of counters and flip-flops, or diodes and capacitors up to now. These methodes are reliable for relative high frequencies, while not credible for reasonable low frequencies or extreme low values. Therefore, we developed the circuit that converts frequencies into DC voltages, into and into log DC values in the wide range from low Hz to several hundred high kHz. We proved their validities through testing them using real data used in nuclear power plant and analyzed their results. And, these methods will be used to measure the neutron level of excore nuclear flux monitoring system in nuclear power plant.