• Journal of KIISE:Information Networking
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• v.36 no.1
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• pp.24-33
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• 2009

In patch-and-stitch localization algorithms, a flip error refers to the kind of error in which a patch is stitched to the map as being wrongly reflected. In this paper, we present an anchor-free localization algorithm which tries to detect and prevent flip errors. The flip error prevention is achieved by two filtering mechanisms: the flip-ambiguity test and the flip-conflict detection. We evaluate the performances of proposed techniques though simulations and show that they achieve significant performance improvements.

• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.4
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• pp.286-291
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• 2013

In this paper, in-line type flip chip bump 3D inspection equipment, using white light interferometer with large F.O.V., which is aimed to be used in flip chip bump test process is developed. Results of flip chip bump height measurement in many substrates and repeatability test results for the bumps in fixed location of each substrate are shown. Test results from test bench and those from developed flip chip bump 3D inspection equipment are compared and as a result repeatability is improved by reducing the impact of system vibration. A valuation basis for the testing quality of flip chip bump 3D inspection equipment is proposed.

• Bulletin of the Korean Chemical Society
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• v.27 no.1
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• pp.87-92
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• 2006

Fas-associated death domain protein (FADD) recruits and activates procaspase-8 through interactions between the death effector domains of these two proteins. Cellular FLICE-inhibitory protein (c-FLIP) was identified as a molecule with sequence homology to caspase-8. It has been postulated that c-FLIP prevents formation of the competent death-inducing signaling complex in a ligand-dependent manner, through its interaction with FADD and/or caspase-8. However, the interaction of FADD and $c-FLIP_s$ (short form) in apoptosis signaling has been controversially discussed. We show the purification and the characterization of human full-length FADD and $c-FLIP_s$ expressed in Escherichia coli. The purified FADD and $c-FLIP_s$ are shown as homogeneity, respectively, in SDS-PAGE analysis and light-scattering measurements. The folding properties of the $\alpha$-helical structure of FADD and the super-secondary structure of $c-FLIP_s$ proteins were characterized by circular dichroism spectroscopy. Furthermore, we report here a series of biochemical and biophysical data for FADD-$c-FLIP_s$ binding in vitro. The binding of both FADD and $c-FLIP_s$ proteins was detected by BIAcore biosensor, fluorescence measurement, and size-exclusion column (SEC).

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.102-106
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• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• 전기의세계
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• v.13 no.3
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• pp.21-27
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• 1964

A method of triggering a series connected complementary transister flip-flop is described. Also measurements have been made for the operation region with respect to the input pulse variation. This circuit is compared with a Eccles-Jordan flip-flop when it used as a Nixie tube driver of a neon lamp driyer.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.907-916
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• 2019

In this paper, we propose a new five-qubit multiple bit flip code that can completely protect the target qubit from all multiple bit flip errors using only CNOT gates. The proposed multiple bit flip codes can be easily extended to multiple phase flip codes by embedding Hadamard gate pairs in the root error section as in conventional single bit flip code. The multiple bit flip code and multiple phase flip code in this paper share the state vector error information by four auxiliary qubits. These four-qubit state vectors reflect the characteristic that all the multiple flip errors with Pauli X and Z corrections commonly include a specific root error. Using this feature, this paper shows that low-cost implementation is possible despite the QECC design for multiple-flip error correction by batch processing the detection and correction of Pauli X and Z root errors with only three CNOT gates. The five-qubit multiple bit flip code and multiple phase flip code proposed in this paper have 100% error correction rate and 50% error discrimination rate. All QECCs presented in this paper were verified using QCAD simulator.

• BMB Reports
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• v.47 no.9
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• pp.488-493
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• 2014

Adaptor protein FADD forms the death inducing signaling complex (DISC) by recruiting the initiating caspases-8 and -10 through homotypic death effector domain (DED) interactions. Cellular FLICE-inhibitory protein (c-FLIP) is an inhibitor of death ligand-induced apoptosis downstream of death receptors, and FADD competes with procaspase-8/10 for recruitment for DISC. However, the mechanism of action of FADD and c-FLIP proteins remain poorly understood at the molecular level. In this study, we provide evidence indicating that the death effector domain (DED) of FADD interacts directly with the death effector domain of human c-FLIP. In addition, we use homology modeling to develop a molecular docking model of FADD and c-FLIP proteins. We also find that four structure-based mutants (E80A, L84A, K169A and Y171A) of c-FLIP DEDs disturb the interaction with FADD DED, and that these mutations lower the stability of the c-FLIP DED.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Journal of Welding and Joining
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• v.20 no.4
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• pp.498-504
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• 2002

Fluxless flip chip bonding process using plasma treatment instead of flux was investigated. The effect of plasma process parameters on tin-oxide etching characteristics were estimated with Auger depth profile analysis. The die shear test was performed to evaluate the adhesion strength of the flip chip bonded after plasma treatment. The thickness of oxide layer on tin surface was reduced after Ar+H2 plasma treatment. The addition of H2 improved the oxide etching characteristics by plasma. The die shear strength of the plasma-treated Sn-Pb solder flip chip was higher than that of non-treated one but lower than that of fluxed one. The difference of the strength between plasma-treated specimen and non-treated one increased with increase in bonding temperature. The plasma-treated flip chip fractured at solder/TSM interface at low bonding temperature while the fracture occurred at solder/UBM interface at higher bonding temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.74-78
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• 2006

This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.