• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.305-311
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• 2005

Flash memory software running on cellular phones and PDAs need to be tested extensively to cope with abrupt power and media faults. For those tests, we designed and implemented a Flash memory emulator with fault injection features. The fault injection tester has provided a helpful framework for designing fault recovery schemes and also for analyzing fault damages to the FTL (Flash Translation Layer) and file system for a Flash memory based system. In this paper, we discuss Plash memory fault types and fault injection features implemented on this Flash memory emulator. We then discuss in detail a design flaw revealed during fault injection tests. Specifically, it was revealed that a scheme that was believed to improve reliability instead, turned out to be harmful. In addition, we discuss post-fault behaviors of the FTL and the file system.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.1-7
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• 2017

As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.21-30
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• 2009

Fusion flash memory such as OneNAND$^{TM}$ is popular as a ubiquitous storage device for embedded systems because it has advantages of NAND and NOR flash memory that it can support large capacity, fast read/write performance and XIP(eXecute-In-Place). Besides, OneNAND$^{TM}$ provides not only advantages of hybrid structure but also multi-block erase function that improves slow erase performance by erasing the multiple blocks simultaneously. But traditional NAND Flash Translation Layer may not fully support it because the garbage collection of traditional FTL only considers a few block as victim block and erases them. In this paper, we propose an Erase Group Flash Translation Layer for improving multi-block erase function. EGFTL uses a superblock scheme for enhancing garbage collection performance and invalid block management to erase multiple blocks simultaneously. Also, it uses clustered hash table to improve the address translation performance of the superblock scheme. The experimental results show that the garbage collection performance of EGFTL is 30% higher than those of traditional FTLs, and the address translation performance of EGFTL is 5% higher than that of Superblock scheme.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.31-38
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• 2015

Nowadays, large size flash memory drives with more than a couple of hundreds of gigabytes are common. This paper presents an efficient cache management scheme of flash translation layer, called TPC-FTL, for large size flash memory drives. Since flash drives of large size usually contain large size RAM, we can enhance the performance of page mapping cache by using more RAM for the cache. But if the size exceeds a threshold, the existing schemes are impractical for real devices, because the time for cache manipulation becomes too long. TPC-FTL manages the cache in translation page unit, not in logical page number unit used in existing schemes. Since a translation page covers a large number of logical page numbers (for example, 512 for 2KB size page), the number of cache elements can be reduced up to a practical level. A performance evaluation shows that average response time, an important performance measure, is better than existing schemes via the effect of utilizing spacial locality in addition to temporal locality.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.94-101
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• 2013

The market for NAND flash-based storage devices has grown significantly as they rapidly replace traditional disk-based storage devices. Heterogeneous NAND flash-based storage devices using both multi-level cell (MLC) and single-level cell (SLC) NAND flash memories are also actively researched since both types of memories complement each other. Heterogeneous NAND flash-based storage devices suffer from the overheads incurred by migration from SLC to MLC and garbage collection of SLC. This paper proposes a new flash translation layer (FTL) for heterogeneous NAND flash-based storage devices to reduce the overheads by utilizing SLC efficiently. The proposed FTL analyzes the access patterns of logical blocks and selects and stores only logical blocks expected to bring performance improvement in SLC. The experimental results show that the total execution time of heterogeneous NAND flash-based storage devices with our proposed FTL scheme is 35% shorter than that with the previously proposed best FTL scheme.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.458-461
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• 2011

모바일 디바이스 저장 장치로 많이 사용되고 있는 플래시 메모리는 가벼운 무게, 내구성, 낮은 전력 소비 등의 장점을 가지고 사용되기 시작하였으며 근래에는 모바일 뿐 아니라 다양한 멀티 미디어 디바이스 전반의 많은 제품에 채용되어 더욱 더 그 범위가 확산되는 추세에 있다. 플래시 메모리는 위에서 언급한 많은 장점이 있지만 기존에 사용되던 디스크와 달리 플래시 메모리 블록을 재사용하기 위해서는 삭제 후 쓰기라는 별도의 연산을 필요로 한다. 이를 FTL (Flash Translation Layer) 이라는 S/W 모듈을 통해 구현되어 있으며 FTL의 구현 알고리즘에 따라 소용되는 연산 비용 또한 상이하며 그 특성과 성능이 매우 다양하게 나타난다. 일반적으로 리눅스에서 FTL은 커널 내부에 구현되어 디바이스 드라이버 형태로 존재하며 일반적인 S/W 개발자보다는 플래시 및 커널 관련 전문지식을 가진 시스템 개발자가 구현을 하게 된다. 이 논문에서는 커널 및 시스템에 대한 깊은 지식 없이도 새롭게 고안된 FTL 알고리즘을 쉽고 빠르게 구현, 검증할 수 있도록 커널이 아닌 사용자 공간에 FTL을 구현하여 빠른 시간 내에 착안된 알고리즘을 실험, 검증할 수 있는 UFTL(User Space Flash Translation Layer) 개발 플랫폼올 제안한다.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.27-35
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• 2021

NAND flash memory-based SSD needs an internal software, Flash Translation Layer(FTL) to provide traditional block device interface to the host because of its physical constraints, such as erase-before-write and large erase block. However, because useful host-side information cannot be delivered to FTL through the narrow block device interface, SSDs suffer from a variety of problems such as increasing garbage collection overhead, large tail-latency, and unpredictable I/O latency. Otherwise, the new type of SSD, open-channel SSD exposes the internal structure of SSD to the host so that underlying NAND flash memory can be managed directly by the host-level FTL. Especially, I/O data classification by using host-side information can achieve the reduction of garbage collection overhead. In this paper, we propose a new scheme to reduce garbage collection overhead of open-channel SSD by separating the journal from other file data for the journaling filesystem. Because journal has different lifespan with other file data, the Write Amplification Factor (WAF) caused by garbage collection can be reduced. The proposed scheme is implemented by modifying the host-level FTL of Linux and evaluated with both Fio and Filebench. According to the experiment results, the proposed scheme improves I/O performance by 46%~50% while reducing the WAF of open-channel SSDs by more than 33% compared to the previous one.

• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.463-475
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• 2009

Flash memory is suitable for real time systems because of its consistent performance for random access, low power consumption and shock resistance. However, flash memory needs blocking time to perform a garbage collection to reclaim invalidated pages. Moreover, the worst-case garbage collection time is significantly longer than the best-case garbage collection time. In this paper, we propose a FTL (Flash Translation Layer) mapping scheme called KAST (K-Associative Sector Translation). In the KAST scheme, user can control the maximum association of the log block to limit the worst-case garbage collection time. Performance evaluation using simulation shows that not only KAST completes the garbage collection within the specified time but also provides about 10~15% better average performance than existing FTL schemes.