• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.318-321
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• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• Journal of the Chungcheong Mathematical Society
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• v.30 no.1
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• pp.77-102
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• 2017

As an analogy of $Poincar{\acute{e}}$ series in the space of modular forms, T. Ono associated a module $M_c/P_c$ for ${\gamma}=[c]{\in}H^1(G,R^{\times})$ where finite group G is acting on a ring R. $M_c/P_c$ is regarded as the 0-dimensional twisted Tate cohomology ${\hat{H}}^0(G,R^+)_{\gamma}$. In the case that G is the Galois group of a Galois extension K of a number field k and R is the ring of integers of K, the vanishing properties of $M_c/P_c$ are related to the ramification of K/k. We generalize this to arbitrary n-dimensional twisted cohomology of the ring of integers and obtain the extended version of theorems. Moreover, some explicit examples on quadratic and biquadratic number fields are given.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.

• Journal of the Chungcheong Mathematical Society
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• v.19 no.4
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• pp.319-324
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• 2006

Let K be a finite cyclic extension of $k=\mathbb{F}_q(T)$ of prime degree ${\ell}$. Let ${\tilde{\mathcal{C}}}l_{K,{\ell}}$ be the Sylow ${\ell}$-subgroup of the ideal class group ${\tilde{\mathcal{C}}}l_K$ of $\mathcal{O}_K$. The structure of ${\tilde{\mathcal{C}}}l_{K,{\ell}}$ as $\mathbb{Z}_{\ell}[G]$/<$N_G$>-module is determined the dimensions $${\lambda}_i\;:=dim_{\mathbb{F}_{\ell}}({\tilde{\mathcal{C}}}l_{K,{\ell}}^{({\sigma}-1)^{i-1}}/{\tilde{\mathcal{C}}}l_{K,{\ell}}^{({\sigma}-1)^i})$$ for $i{\geq}1$. In this paper we investigate the dimensions ${\lambda}_1$ and ${\lambda}_2$.

• Bulletin of the Korean Mathematical Society
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• v.54 no.5
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• pp.1779-1801
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• 2017

Let X be a minimal del Pezzo surface of degree 2 over a finite field ${\mathbb{F}}_q$. The image ${\Gamma}$ of the Galois group Gal(${\bar{\mathbb{F}}}_q/{\mathbb{F}}_q$) in the group Aut($Pic({\bar{X}})$) is a cyclic subgroup of the Weyl group W($E_7$). There are 60 conjugacy classes of cyclic subgroups in W($E_7$) and 18 of them correspond to minimal del Pezzo surfaces. In this paper we study which possibilities of these subgroups for minimal del Pezzo surfaces of degree 2 can be achieved for given q.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.6
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• pp.17-28
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• 2002

XTR is a new method to represent elements of a subgroup of a multiplicative group of a finite field GF( $p^{6m}$) and it can be generalized to the field GF( $p^{6m}$)$^{[6,9]}$ This paper progress optimal extention fields for XTR among Galois fields GF ( $p^{6m}$) which can be aplied to XTR. In order to select such fields, we introduce a new notion of Generalized Opitimal Extention Fields(GOEFs) and suggest a condition of prime p, a defining polynomial of GF( $p^{2m}$) and a fast method of multiplication in GF( $p^{2m}$) to achieve fast finite field arithmetic in GF( $p^{2m}$). From our implementation results, GF( $p^{36}$ )longrightarrowGF( $p^{12}$ ) is the most efficient extension fields for XTR and computing Tr( $g^{n}$ ) given Tr(g) in GF( $p^{12}$ ) is on average more than twice faster than that of the XTR system on Pentium III/700MHz which has 32-bit architecture.$^{［6,10］/ ［6,10］/6,10］}$

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.892-897
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• 2008

In this paper, a new architecture for digit-parallel/bit-serial GF$(2^m)$ multiplier with low latency is proposed. The proposed multiplier operates in polynomial basis of GF$(2^m)$ and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.190-194
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• 2002

Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.