• Title/Summary/Keyword: fine pitch

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Development of Multi-Axis Control Program for Long Range AFM Using an FPGA Module (FPGA 모듈을 이용한 Long Range AFM용 다축 제어 프로그램 개발)

  • Lee J.Y.;Eom T.B.;Kim J.W.;Kang C.S.;Kim J.A.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2006.05a
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    • pp.289-290
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    • 2006
  • In general, atomic force microscope (AFM) used for metrological purpose has measuring range less than a few hundred micrometers. We design and fabricate an AFM with long measuring range of $200mm{\times}200mm$ in X and Y axes. The whole stage system is composed of surface plate, global stage, microstage. By combining global stage and microstage, the fine and long movement can be provided. We measure the position of the stage and angular motions of the stage by laser interferometer. A piezoresistive type cantilever is used for compact and long term stability and a flexure structure with PZT and capacitive sensor is used for Z axis feedback control. Since the system is composed of various actuators and sensors, a real time control program is required for the implementation of AFM. Therefore, in this work, we designed a multi-axis control program using a FPGA module, which has various functions such as interferometer signal converting, PID control and data acquisition with triggering. The control program achieves a loop rate more than 500 kHz and will be applied for the measurement of grating pitch and step height.

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Reflow properties of the lead-free solder with low melting temperature (저온 접합용 무연 솔더의 reflow 공정 특성)

  • Yu, A-Mi;Jang, Jae-Won;Kim, Mok-Soon;Lee, Jong-Hyun;Kim, Jun-Ki
    • Proceedings of the KWS Conference
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    • 2009.11a
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    • pp.76-76
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    • 2009
  • 눈부신 전자산업의 발달로 대부분의 전자제품이 다기능/경박단소화 되고 있어, 고밀도 실장 기술인 양면 표면실장과 고집적 패키징 기술인 패키지 적층 공정의 적용이 점차 확대되고 있다. 따라서 양면 표면실장 및 패키지 적층 공정에 사용되는 저온 접합용 무연 솔더 즉, $183^{\circ}C$(Sn-37Pb 공정 솔더 융점) 이하의 융점을 가지는 저온 무연 솔더에 대한 관심이 높아지고 있다. 한편, 미세피치 적용 분야에 있어 ACF/P를 이용한 COG 접속 분야 외에도 최근 저온 접합용 무연 솔더를 이용한 접속 분야가 각광을 받고 있다. 따라서, 접속피치 미세화에 대응하기 위해 스크린 인쇄성을 향상시킬 수 있는 저온 무연 솔더 paste 제조 및 공정 기술의 개발이 필요한 실정이다. 현재 대표적인 저온 무연 솔더 조성은 Sn-Bi계($138^{\circ}C$ 융점)와 Sn-In계($120^{\circ}C$ 융점)이다. 하지만, 이들 조성의 신뢰성 등에 있어 개선의 여지가 있으므로 이를 해결하기 위한 무연솔더 조성의 개발이 필요하다. 이와 같은 관점에서, 본 연구는 $137^{\circ}C$의 융점을 갖는 Sn-57.6Ag-0.4Ag 저온 무연 솔더 paste를 $217^{\circ}C$의 융점을 갖는 Sn-3.0Ag-0.5Cu 솔더 paste와 비교하여 인쇄성, reflow 특성, void inspection, 미세조직 관찰 및 underfill 적용 등의 실험을 실시하였다.

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Morphological optimization of process parameters of randomly oriented carbon/carbon composite

  • Raunija, Thakur Sudesh Kumar;Manwatkar, Sushant Krunal;Sharma, Sharad Chandra;Verma, Anil
    • Carbon letters
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    • v.15 no.1
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    • pp.25-31
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    • 2014
  • A microstructure analysis is carried out to optimize the process parameters of a randomly oriented discrete length hybrid carbon fiber reinforced carbon matrix composite. The composite is fabricated by moulding of a slurry into a preform, followed by hot-pressing and carbonization. Heating rates of 0.1, 0.2, 0.3, 0.5, 1, and $3.3^{\circ}C/min$ and pressures of 5, 10, 15, and 20 MPa are applied during hot-pressing. Matrix precursor to reinforcement weight ratios of 70:30, 50:50, and 30:70 are also considered. A microstructure analysis of the carbon/carbon compacts is performed for each variant. Higher heating rates give bloated compacts whereas low heating rates give bloating-free, fine microstructure compacts. The compacts fabricated at higher pressure have displayed side oozing of molten pitch and discrete length carbon fibers. The microstructure of the compacts fabricated at low pressure shows a lack of densification. The compacts with low matrix precursor to reinforcement weight ratios have insufficient bonding agent to bind the reinforcement whereas the higher matrix precursor to reinforcement weight ratio results in a plaster-like structure. Based on the microstructure analysis, a heating rate of $0.2^{\circ}C/min$, pressure of 15 MPa, and a matrix precursor to reinforcement ratio of 50:50 are found to be optimum w.r.t attaining bloating-free densification and processing time.

Mechanical design of mounts for IGRINS focal plane array

  • Oh, Jae Sok;Park, Chan;Cha, Sang-Mok;Yuk, In-Soo;Park, Kwijong;Kim, Kang-Min;Chun, Moo-Young;Ko, Kyeongyeon;Oh, Heeyoung;Jeong, Ueejeong;Nah, Jakyuong;Lee, Hanshin;Pavel, Michael;Jaffe, Daniel T.
    • The Bulletin of The Korean Astronomical Society
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    • v.39 no.1
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    • pp.53.2-53.2
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    • 2014
  • IGRINS, the Immersion GRating INfrared Spectrometer, is a near-infrared wide-band high-resolution spectrograph jointly developed by the Korea Astronomy and Space Science Institute and the University of Texas at Austin. IGRINS employs three HAWAII-2RG focal plane array (FPA) detectors. The mechanical mounts for these detectors serves a critical function in the overall instrument design: Optically, they permit the only positional compensation in the otherwise "build to print" design. Thermally, they permit setting and control of the detector operating temperature independently of the cryostat bench. We present the design and fabrication of the mechanical mount as a single module. The detector mount includes the array housing, a housing for the SIDECAR ASIC, a field flattener lens holder, and a support base. The detector and ASIC housing will be kept at 65 K and the support base at 130 K. G10 supports thermally isolate the detector and ASIC housing from the support base. The field flattening lens holder attaches directly to the FPA array housing and holds the lens with a six-point kinematic mount. Fine adjustment features permit changes in axial position and in yaw and pitch angles. We optimized the structural stability and thermal characteristics of the mount design using computer-aided 3D modeling and finite element analysis. Based on the computer simulation, the designed detector mount meets the optical and thermal requirements very well.

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Optimization of Thermal Deformation in Probe Card (프로브 카드의 열변형 최적화)

  • Chang, Yong-Hoon;Yin, Jeong-Je;Suh, Yong-S.
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.11
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    • pp.4121-4128
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    • 2010
  • A probe card is used in testing semiconductor wafers. It must maintain a precise location tolerance for a fine pitch due to highly densified chips. However, high heat transferred from its lower chuck causes thermal deformations of the probe card. Vertical deformation due to the heat will bring contact problems to the pins in the probe card, while horizontal deformation will cause positional inaccuracies. Therefore, probe cards must be designed with proper materials and structures so that the thermal deformations are within allowable tolerances. In this paper, heat transfer analyses under realistic loading conditions are simulated using ANSYS$^{TM}$ finite element analysis program. Thermal deformations are calculated based on steady-state temperature gradients, and an optimal structure of the probe card is proposed by adjusting a set of relevant design parameters so that the deformations are minimized.

A pin type current probe using Planar Hall Resistance magnetic sensor (PHR 자기센서를 적용한 탐침형 전류 프로브)

  • Lee, Dae-Sung;Lee, Nam-Young;Hong, Sung-Min;Kim, CheolGi
    • Journal of Sensor Science and Technology
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    • v.30 no.5
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    • pp.342-348
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    • 2021
  • For the characterization or failure analysis of electronic devices such as PCB (printed circuit boards), the most common method is the measurement of voltage waveforms with an oscilloscope. However, because there are many types of problems that cannot be detected by voltage waveform analysis, several other methods such as X-ray transmission, infrared imaging, or eddy current measurement have been applied for these analyses. However, these methods have also been limited to general analyses because they are partially useful in detecting physical defects, such as disconnections or short circuits. Fundamentally current waveform measurements during the operation of electronic devices need to be performed, however, commercially available current sensors have not yet been developed, particularly for applications in highly integrated PCB products with sub-millimeter fine pitch. In this study, we developed a highly sensitive PHR (planar hall resistance) magnetic sensor for application in highly integrated PCBs. The developed magnetic sensor exhibited sufficient features of an ultra-small size of less than 340 ㎛, magnetic field resolution of 10 nT, and current resolution of 1 mA, which can be applicable for PCB analyses. In this work, we introduce the development process of the magnetic sensing probe and its characteristic results in detail, and aim to extend this pin-type current probe to applications such as current distribution imaging of PCBs.

Effect of Ag Nanolayer in Low Temperature Cu/Ag-Ag/Cu Bonding (저온 Cu/Ag-Ag/Cu 본딩에서의 Ag 나노막 효과)

  • Kim, Yoonho;Park, Seungmin;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.28 no.2
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    • pp.59-64
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    • 2021
  • System-in-package (SIP) technology using heterogeneous integration is becoming the key of next-generation semiconductor packaging technology, and the development of low temperature Cu bonding is very important for high-performance and fine-pitch SIP interconnects. In this study the low temperature Cu bonding and the anti-oxidation effect of copper using porous Ag nanolayer were investigated. It has been found that Cu diffuses into Ag faster than Ag diffuses into Cu at the temperatures from 100℃ to 200℃, indicating that solid state diffusion bonding of copper is possible at low temperatures. Cu bonding using Ag nanolayer was carried out at 200℃, and the shear strength after bonding was measured to be 23.27 MPa.

Technology Trends of Semiconductor Package for ESG (ESG를 위한 반도체 패키지 기술 트렌드)

  • Minsuk Suh
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.35-39
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    • 2023
  • ESG (Environment, Social, Governance) has become a major guideline for many companies to improve corporate value and enable sustainable management. Among them, the environment requires a technological approach. This is because technological solutions are needed to reduce or prevent environmental pollution and save energy. Semiconductor package technology has been developed to better satisfy the essential roles of semiconductor packaging: chip protection, electrical/mechanical connection, and heat dissipation. Accordingly, technologies have been developed to improve heat dissipation effect, improve electrical/mechanical properties, improve chip protection reliability, stacking and miniaturization, and reduce costs. Among them, heat dissipation technology increases thermal efficiency and reduces energy consumption for cooling. Also, technology to improve electrical characteristics has had an impact on the environment by reducing energy consumption. Technologies that recycling or reducing material consumption reduce environmental pollution. And technologies that replace environmentally harmful substances contribute to environmental improvement, in particular. In this paper, I summarize trends in semiconductor package technologies to prevent pollution and improve environment.

Advancements in Bonding Technologies for Flexible Display Driver IC(DDI) Packaging (Flexible DDI Package의 Bonding 기술 발전)

  • Kyeong Tae Kim;Yei Hwan Jung
    • Journal of the Microelectronics and Packaging Society
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    • v.31 no.3
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    • pp.10-17
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    • 2024
  • This paper discusses Chip On Film (COF) technology, one of the key technologies in flexible packaging to enable miniaturization and flexibility of electronic devices. COF attaches Display Driver IC (DDI) directly to a flexible polyimide substrate, enabling lightweight and reduced thickness for high-resolution displays. COF technology is primarily used in high-performance display panels, such as organic light emitting diode (OLED) displays, and plays a key role in portable electronic devices, such as smartphones and wearable devices. This study analyzes the key components of COF and advances in bonding technology. In particular, the introduction of modern bonding techniques, such as thermo-compression bonding and thermo-sonic bonding, has led to significant improvements in bonding reliability and electrical performance. These bonding techniques enhance the mechanical stability of COF packages while maintaining high electrical connectivity in fine-pitch structures. This paper will discuss the future development of COF bonding technology and its challenges and explore its potential as a next-generation display and advanced packaging technology.

Chip-to-chip Bonding with Polymeric Insulators (고분자 절연체를 이용한 칩투칩 본딩)

  • Ye Jin Oh;Seongwoo Jeon;Jin Su Shin;Kee-Youn Yoo;Hyunsik Yoon
    • Journal of the Microelectronics and Packaging Society
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    • v.31 no.3
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    • pp.87-90
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    • 2024
  • Currently, when oxides are used as insulators in hybrid bonding for 3D integration, they are prone to delamination due to their surface characteristics, and the RC delay value due to the resistance of the metal and the capacitance of the insulator increases as the wiring of the semiconductor chip becomes longer. To solve these problems, we studied the optimization of the conditions of the polymer insulator bonding method for hybrid bonding. To check the possibility of the de-wetting method, we coated a polymer film on the existing micro pillar and conducted hot-press bonding to remove the polymer between the metals. Through this study, it is expected that the introduction of polymers as insulators in hybrid bonding and fine-pitch metal bonding will improve signal transmission speed by reducing RC delay. It is also expected to be commercialized in the future to increase the number of I/O terminals by applying it to hybrid bonding.