• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.111-114
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• 2008

We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at $180^{\circ}C$. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 nm to 200 nm, the grain size was increased from 20 nm to 40 nm. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 nm are 26, 77 and $119\;cm^2/Vsec$, respectively. The leakage current, however, is increased from $7.2{\times}10^{-10}$ to $1.9{\times}10^{-8}\;A$ at $V_{GS}=-4.4\;V$ when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1341-1342
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• 2006

Electrical characteristics of field-effect thin film transistors (TFTs) with p-channels of CdTe/CdHgTe core-shell nanocrystals are investigated in this paper. For the fabrication of bottom- and top-gate TFTs, CdTe/CrHgTe nanocrystals synthesized by colloidal method are first dispersed on oxidized p+ Si substrates by spin-coating, the dispersed nanoparticles are sintered at $150^{\circ}C$ to form the channels for the TFTs, and $Al_{2}O_{3}$ layers are deposited on the channels. A representative bottom-gate field-effect TFT with a bottom-gate $SiO_2$ layer exhibits a mobility of $0.21cm^2$/ Vs and an Ion/Ioff ratio of $1.5{\times}10^2$ and a representative top-gate field-effect TFT with a top-gate $Al_{2}O_{3}$ layer provides a field-effect mobility of $0.026cm^2$/ Vs and an Ion/Ioff ratio of $2.5{\times}10^2$. $Al_{2}O_{3}$ was deposited for passivation of CdTe/CdHgTe core-shell nanocrystal layer, resulting in enhanced hole mobility, Ior/Ioff ratio by 0.25, $3{\times}10^3$, respectively. The CdTe/CdHgTe nanocrystal-based TFTs with bottom- and top gate geometries are compared in this paper.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.238.2-238.2
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• 2011

Organic thin film transistors (OTFTs) have been attracting considerable attention because of their potential use in low-cost, large area, electronic devices such as flexible displays, biochemical sensors, and smart cards. In past several years, gold/pentacene has been frequently used in OTFTs because of the high mobility of pentacene and the high work function of gold. To improve the performance of the OTFTs contact area doping of pentacene with p-doping materials are well known. In this work we demonstrated selectively contact area doping of pentacene with Iodine vapor. For effective doping elevated pentacene layer under the source-drain area was deposited and exposed to Iodine vapor. We got better electrical performance for elevated pentacene structure rather than planer structure with relatively high field-effect mobility.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.303-304
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• 2009

We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine. ($F_{16}CuPc$) as an active layer. And we observed the surface morphology of the $F_{16}CuPc$ thin film. The $F_{16}CuPc$ thin film thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility.

• Transactions on Electrical and Electronic Materials
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• 제8권4호
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• pp.170-173
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• 2007

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated the organic field-effect transistor based a copper phthalocyanine (CuPc) as an active layer on the silicon substrate. The CuPc FET device was made a topcontact type and the substrate temperature was room temperature and $150^{\circ}C$. The CuPc thickness was 40 nm, and the channel length was $50{\mu}m$, channel width was 3 mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in CuPc FET and we calculated the effective mobility with each device. Also, we observed the AFM images with different substrate temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.598-601
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• 1999

There is currently considerable interest in the applications of conjugated polymers, oligomers and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field effect transistor and light emitting didoes. In this study, Pentacene thin film transistors(TFTs) were fabricated on glass substrate. Aluminum and Gold wei\ulcorner used fur the gate and source/drain electrodes. Silicon dioxde was deposited as a gate insulator by PECVD and patterned by R.I.E. The semiconductor layer of pentacene was thermally evaporated in vaccum at a pressure of about 10$^{-8}$ Torr and a deposition rate 0.3$\AA$/sec. The fabricated devices exhibited the field-effect mobility as large as 0.07cm$^2$/Vs and on/off current ratio larger than 10$^{7}$

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.164-168
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• 2005

We report high performance poly (3-hexylthiophene) organic field-effect transistors fabricated on a plastic substrate. The polymer active channel layer was directly printed by the rubber stamp printing method with a pre-patterned elastomer stamp. As a result. organic transistors having average field-effect mobility of 0.079 $cm^2/Vs$ and on/off ratio of $10^4{\sim}10^5$ were realized on a plastic substrate. Also, through the investigation of the molecular ordering of rubber-stamp-printed poly (3-hexylthiophene) films using synchrotron grazing-incidence X-ray diffraction measurements, the films were found to have edge-on structure which is favorable in realizing high performance organic transistors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.450-453
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• 1999

In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.

• Electronic Materials Letters
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• 제14권6호
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• pp.774-783
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• 2018

Full maximum-entropy mobility-spectrum analysis (FMEMSA) is the best algorithm among mobility spectrum analyses by which we can obtain a set of partial-conductivities associated with mobility values (mobility spectrum) by analyzing magnetic-field-dependent conductivity-tensors. However, it is restricted to a direct band-gap semiconductor and should be modified for materials with other band structures. We developed the modified version of FMEMSA which is appropriate for a material with a single anisotropic valley, or an indirect-band-gap semiconductor quantum-well with a single non-degenerate conduction-band valley e.g., (110)-oriented AlAs quantum wells with a single anisotropic valley. To demonstrate the reliability of the modified version, we applied it to several sets of synthetic measurement datasets. The results demonstrated that, unlike existing FMEMSA, the modified version could produce accurate mobility spectra of materials with a single anisotropic valley.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.