• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.1-14
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• 2001

Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.140-141
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• 2007

To fabricate the metal-ferroelectric-insulator-semiconductor (MFIS) structure for the ferroelectric random access memory (FRAM) application, we prepared the ferroelectric $Sr_{0.9}Bi_{2.1}Ta_2O_9$ (SBT) and the insulator LaZrOx (LZO) thin films on the silicon substrate using a sol-gel method. In this study, we will investigate the feasibility of the SBT/LZO/Si structure as one of the promising gate configuration for the 1-transistor (1-T) type FRAM, by measurements of the electrical properties and the physical properties.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.89-89
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• 2003

• Journal of IKEEE
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• v.26 no.2
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• pp.329-332
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• 2022

In this paper, retention characteristics of lateral charge migration according to parameters of 3D NAND flash memory to which ferroelectric (HfO₂) structure is applied and ∆V_th were analyzed. The larger the P_s, the greater maximum polarization possible in ferroelectric during Programming. Therefore, the initial V_th increases by about 1.04V difference at P_s 70µC/cm² than at P_s 25µC/cm². Also, electrons trapped after the Program operation causes lateral charge migration over time. Since ferroelectric maintains polarization without applying voltage to the gate after Programming, regardless of P_s value, polarization increases as P_r increases and the ∆V_th due to lateral charge migration becomes smaller by about 1.54V difference at P_r 50µC/cm² than P_r 5µC/cm².

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.83-89
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• 1989

Ferroelectric $PbTiO_3$ thin film is deposited with rf sputtering at substrate temperature of $100-150^{\circ}C$. It is found that this has pyrochlore structure of amorphous type by X-ray diffractive analysis. Thermal annealing has excellent characteristics at $550^{\circ}C$ and laser annealing has best crystalline structure in case of scanning with 50 watts. Interface states in MFST and MFOST structure with a $PbTiO_3$ ferroelectric thin film gate have been investigated from analysis of C-V data. The interface states density has been drastically reduced by inserting an oxide layer between ferroelectric and semiconductor. The observed effect increase feasibility of employing ferroelectric thin films such as nonvolatile memory field effect transistor, IR optical FET, and Image Devices with a ferroelectric layer.

• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.40-44
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• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.433-436
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• 1999

In this paper we applied TVS(Triangular Voltage Sweep) method to calculate the mobile ionic charge densities in some ferroelectric thin films. During the measurement, the temperature of specimens were maintained at 20$0^{\circ}C$. By this method, the amount of mobile ionic charge Q$_{m}$ and mobile ionic charge density N$_{m}$ of a MFIS structure were calculated 3.5 [pC] and about 4.3$\times$10$^{11}$ [ions/cm$^2$], respectively. In order to successful TVS measurement, the gate leakage current density of films must be low 10$^{-9}$ (A/cm$^2$) order.der.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.73-77
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• 2023

In this study, we developed a Multi-level FeRAM (Ferroelectrics random access memory) device utilizing different ferroelectric materials and analyzed its operation through C-V analysis using simulations. To achieve Multi-level operation, we proposed an MFM (Multi-Ferroelectric Material) structure by depositing two different ferroelectric materials with distinct properties horizontally on the same bottom electrode and subsequently adding a gate electrode on top. By analyzing C-V peaks based on the polarization phenomenon occurring under different voltage conditions for the two materials, we confirmed the feasibility of achieving Multi-level operation, where either one or both of the materials can be polarized. Furthermore, we validated the process for implementing the proposed structure using semiconductor fabrication through process simulations. These results signify the significance of the new structure as it allows storing multiple states in a single memory cell, thereby greatly enhancing memory integration.