• Journal of the Korean Chemical Society
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• v.39 no.6
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• pp.459-465
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• 1995

Acetolactate Synthase (ALS) was partially purified from the yeast and its basic biochemical studies were carried out. Yeast was grown in the minimum media containing 0.5% glucose, 51 mM $K_2HPO_4$, 22 mM $KH_2PO_4$, 8 mM $(NH_4)2SO_4,\;0.4\;m M\;MgSO_4$ for 18 hours at 37 $^{\circ}C$. The cell was ruptured in the buffer (20 mM phosphate buffer pH 7.0, 0.1 mM TPP, 0.5 mM DTT, 1 ${\mu}M$ FAD, and 1 mM MgCl_2$) following an overnight suspension. The supernatant fraction was collected from $10,000{\times}g$ and the enzyme was further purified by ammonium sulfate fractionation, DEAE-Sephacel chromatography and leucine-agarose chromatography. The enzyme activity was measured under the various conditions by the function of protein concentration, time, temperature, pH, and substrate. The optimum temperature was found to be 50$^{\circ}C$, optimum pH 8.0∼8.5. The kinetic parameters, $K_m\;and\;V_{max}$ were 8.4 mM and 17.9 nmol/mg/min respectively. Stability of the enzyme was studied with ethylene glycol and glycerol added to the enzyme solution. Both ethylene glycol and glycerol improved the enzyme stability up to 50%. The study of feedback inhibition showed that valine was a strong inhibitor while leucine was a weak inhibitor.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.4
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• pp.1768-1789
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• 2016

In contemporary video streaming systems based on HTTP protocol, video players at the client side are responsible for adjusting video quality to network conditions and user expectations. However, when multiple video clips are streamed simultaneously, an intricate application logic implemented in the video players overlays the TCP mechanism which is responsible for a balanced access to a shared network link. As a result, some video players may not obtain a fair share of network throughput and may be vulnerable to an unstable video bit-rate. Therefore, we propose to simplify the algorithms implemented in the video players, which are responsible for the adjustment of video quality and constrain their functionality only to sending feedback to a server about a state of the player buffer. The main logic of the system is shifted to the server, which is now responsible for bit-rate selection and prioritisation of the video streams transmitted to multiple clients. To verify our proposition, we performed several experiments in a laboratory environment which show that when the server cooperates with the clients, the video players experience fewer quality switches and the system achieves better fairness when allocating network throughput among the video players. However, this comes at the cost of worse utilisation of network bandwidth.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.155-162
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• 1999

Various applications of video conferencing are required real-time transmission in order to offer service of best effort in internet. Because the bandwidth of internet changes dynamically, appropriated QoS could not be guaranteed To resolve the problem. available bandwidth between sender and receiver is measured. And according to measured bandwidth, the transmission of multimedia data is controlled In this paper, we propose algorithm of efficient transmission for best QoS in internet According to a present status of network, we measure available bandwidth using feedback RTCP information and change a compression rate to reduce a producing CODEC data. And according to the priority that is measured by packet loss for received RTCP information, we abandon frames indicated as lower weight in transmission buffer of sender.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.215-217
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• 2005

There are two types of packet loss probabilities used in both the network layer and the physical layer within the wireless transmitter such as a queueing discard probability and transmission loss probability. We analyze these loss performances in order to guarantee Quality of Service (QoS) which is the basic of the future network. The queuing loss probability is caused by a maximum allowable delay time and the transmission loss probability is caused by a wireless channel error. These two types of packet loss probabilities are not easily analyzed due to recursive feedback which, originates as a result at a queueing delay and a number of retransmission attempts. We consider a wireless transmitter to a M/D/1 queueing model. We configurate the model to have a finite-size FIFO buffer in order to analyze the real-time traffic streams. Then we present the approaches used for evaluating the loss probabilities of this M/D/1/K queueing model. To analyze the two types of probabilities which have mutual feedbacks with each other, we drive the solutions recursively. The validity and accuracy of the analysis are confirmed by the computer simulation. From the following solutions, we suggest a minimum of 'a Maximum Allowable Delay Time' for real-time traffic in order to initially guarantee the QoS. Finally, we analyze the required service rate for each type utilizing real-time traffic and we apply our valuable analysis to a N-user's wireless network in order to get the fundamental information (types of supportable real-type traffics, types of supportable QoS, supportable maximum number of users) for network design.