• Journal of IKEEE
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• v.26 no.3
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• pp.462-467
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• 2022

The feedback buffer structure is proposed to alleviate the overshoot and undershoot phenomenon and the regulation of the output voltage. The conventional LDO regulator undergoes a regulation voltage change caused by a constant load current change. An LDO regulator with a feedback voltage sensing structure operates in the input voltage range of 3.3 to 4.5 V and has a load current of up to 150 mA at output voltage of 3 V. According to the simulation results, a regulation value of 6.2 mV was ensured when the load current uniformly changed to 150 mA.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.829-832
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• 2007

A high-speed and accurate analog buffer is proposed for mobile display using LTPS TFTs. The proposed analog buffer is common source type with sampling and negative feedback mode. Therefore, driving speed of the proposed buffer is faster than previously reported one. In addition, the accuracy is very high because of high negative feedback gain. The simulation results show that maximum mischarging voltage of the proposed buffer is 8mV and previously reported one is 37mV. And Power consumption of the proposed buffer is $43.1{\mu}W$, which is 73% of previously reported one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5A
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• pp.514-520
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• 2004

In WDM networt a WDM buffer is one of essential elements for realizing all-optical packet switching system. In this paper, we propose and demonstrate a single loop type all-optical WDM buffer system. The proposed one consists of NOLM and feedback loop, and provides more than 40 turns buffering (more than 20${\mu}\textrm{s}$) for single input pulse (1550nm, width: 20㎱) before selected by control signal pulse (1553nm, width: 30㎱).

• Journal of the Korea Computer Industry Society
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• v.3 no.9
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• pp.1251-1260
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• 2002

Real-time application programs have synchronization constraints which need to be met between media-data. Synchronization method represents feedback method including virtual client-side buffer. This buffer is used in buffer level method. It is client-leading synchronization that is absorbing variable transmission delay time and that is synchronizing by feedback control. It is the important factor for playback rate and QoS if the buffer level is normal or not. To solve the problems, we can control the start of transmission in multimedia server by appling filtering, control and network evaluation function. Synchronization method is processing for smooth presentation without cut-off while media is playing out. When audio frame which is master media is in high threshold buffer level we decrease play out time gradually, otherwise we increase it slowly.

• The KIPS Transactions:PartB
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• v.11B no.6
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• pp.625-632
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• 2004

Since the H.264 encoding adopts both forward prediction and hi-direction prediction modes and exploits Variable Length Coding(VLC), the amount of data generated from video encoder varies as Flaying time goes by. The fixed bit rate encoding system which has limited transmission channel capacity uses a buffer to control output bitstream It's necessary to control the bitstream to maintain within manageable range so as to protect buffer from overflow or underflow. With existing bit amount control algorithms, the $\lambda_{MODE}$ which is relationship between distortion value and quantization parameter often excesses normal value to end up with video error. This paper proposes an algorithm to protect buffer from overflow or underflow by introducing a new quantization parameter against distortion value of H.264 video data. The test results of 6 exemplary data show that the proposed algorithm has the same PSNR as and up to 8% reduced bit rate against existing algorithms.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.179-182
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• 2003

A simulation on bootstrapping circuit has been performed by modelling a coaxial cable as a transmission line. It is shown that the bootstrapping circuit could be unstable due to the transmission line effect though an ideal amplifier is used. While the conventional bootstrapping circuit does not cancel the input capacitance of the input buffer, a new bootstrapping circuit that cancels input capacitance of the input buffer has been proposed. The proposed bootstrapping circuit consists of the input buffer of which gam is larger than 1 and a feedback resistor to control the loop gain. The proposed bootstrapping circuit has higher input impedance than that of the conventional circuit.

• The KIPS Transactions:PartC
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• v.9C no.6
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• pp.953-960
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• 2002

Rel-time application programs have constraints which need to be met between media-data. It is client-leading synchronization that is absorbing variable transmission delay time and that is synchronizing by feedback control and palyout control. It is the important factor for playback rate and QoS if the buffer level is normal or not. This paper, The method of maintenance buffer normal state transmits in multimedia server by appling feedback of filtering function. And synchronization method is processing adaptive playout time for smooth presentation without cut-off while media frame is skip. When audio frame which is master media is in upper threshold buffer level we decrease play out time gradually, low threshold buffer level increase it slowly.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.