• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.603-609
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• 2003

Adaptive routing methods are studied for effective routing in many topologies where occurrence of the faulty nodes are inevitable. Mesh topology provides simplicity in implementing these methods. Many routing methods for mesh are able to tolerate a large number of faults enclosed by a rectangular faulty block. But they consider even good nodes in the faulty block as faulty nodes. Hence, it results the degradation of node utilization. This problem is solved by a method which transmits messages to destinations within faulty blocks via multiple “intermediate nodes”. It also divides faulty block into multiple expanded meshes. With these expanded meshes, DAG(Directed Acyclic Graph) is formed and a message is able to be routed by the shortest path according to the DAG. Therefore, the additional number of hops can be resulted. We propose a method that reduces the number of hops by searching direct paths from the destination node to the border of the faulty block. This path is called SCP(Short-Cut Path). If the path and the traversing message is on the same side of outside border of the faulty block, the message will cut into the path found by our method. It also reduces the message traverse latency between the source and the destination node.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.23-29
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• 2010

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.15-25
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• 2011

A differential fault analysis(DFA) is one of the most important side channel attacks on block ciphers. Most block ciphers, such as DES, AES, ARIA, SEED and so on., have been analysed by this attack. In 2008, Wei et al. proposed the first DFA on ARIA-128. Their attack can recover the 128-bit secrey key by about 45 faulty ciphertexts. In this paper, we propose an improved DFA on ARIA-128. We can recover the 12S-bit secret key by only 4 faulty ciphertexts with the computational complexity of O($2^{32}$).

• Proceedings of the Optical Society of Korea Conference
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• 2004.07a
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• pp.64-67
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• 2004

The optics and opto-mechanics are disigned for imaging the sun at Lyman-${\alpha}$ line for scientific satellite. The optics are composed of conic mirrors. In order to block stary light. the new baffle design method is suggested. And we will present the opto-mechanics for this scientific satellite.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1022-1032
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• 2002

A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.5
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• pp.1071-1078
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• 2018

Recently, a family of lightweight block ciphers CHAM that has effective performance on resource-constrained devices is proposed. The CHAM uses a stateless-on-the-fly key schedule method which can reduce the key storage areas. Furthermore, the core design of CHAM is based on ARX(Addition, Rotation and XOR) operations which can enhance the computational performance. Nevertheless, we point out that the CHAM algorithm may be vulnerable to the fault injection attack which can reveal 4 round keys and derive the secret key from them. As a simulation result, the proposed fault injection attack can extract the secret key of CHAM-128/128 block cipher using about 24 correct-faulty cipher text pairs.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.5
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• pp.167-174
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• 2009

Recently, Li et al. proposed a new differential fault analysis(DFA) attack on the block cipher ARIA using about 45 ciphertexts. In this paper, we apply their DFA skill on AES and improve attack method and its analysis. The basic idea of our DFA method is that we recover intermediate ciphertexts in last round using final faulty ciphertexts and find out last round secret key. In addition, we present detail DFA procedure on AES and analysis of complexity. Furthermore computer simulation result shows that we can recover its 128-bit secret key by introducing a correct ciphertext and 2 faulty ciphertexts.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.371-381
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• 2013

An encryption algorithm is executed to supply data confidentiality using a secret key which is embedded in a crypto device. However, the fault injection attack has been developed to extract the secret key by injecting errors during the encryption processes. Especially, an attacker can find the secret key of block cipher ARIA using about 33 faulty outputs. In this paper, we proposed a countermeasure resistant to the these fault injection attacks by checking the difference value between input and output informations. Using computer simulation, we also verified that the proposed countermeasure has excellent fault detection rate and negligible computational overhead.

• Transactions of the Korean Society of Automotive Engineers
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• v.25 no.2
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• pp.149-156
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• 2017

Various kinds of accessories(e.g., clock, radio, automatic door locks, alarm devices, etc.) or unit components (e.g., black box, navigation system, alarm, private audio, etc.) require dark current even when the vehicle power is turned off. However, accessories or unit components can be the causes of excessive dark current generation. It results in battery discharge and the vehicle's failure to start. Therefore, immediate detection of abnormal dark current and response are very important for a successful repair job. In this paper, we can increase the maintenance efficiency by presenting a standardized diagnostic process for the measurement of the dark current and the existing problem. As a result of the absence of a system to block the dark current in a vehicle, diagnosis and repair were performed immediately by using a standardized dark current diagnostic process.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.85-91
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• 1993

In this paper, we propose the test pattern generation algorithm of the embedded faulty MUX for the prevention of misdiagnosis of digital systems. When the system is partitioned with a large number of functional blocks, if the faults are exsisted in a embedded MUX then it can not diagnose the wanted observation of functional block. The proposed test pattern generstion algorithm can apply the MUXs that designd 2-level and multi-level both. Fault coverage becomes 100% and so it is no necessary of the additional fault simulation and the proposed algorithm that have the regulary and easily generated 2d test patterns. And we confirmed that the reduction of test cost becomes 85%, compared with the conventional segmentation testing scheme.