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Parallel I/O DRAM BIST for Easy Redundancy Cell Programming  

유재희 (홍익대학교 전자전기공학부)
하창우 (삼성전기 기술총괄연구소)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.12, 2002 , pp. 1022-1032 More about this Journal
Abstract
A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.
Keywords
DRAM; BIST;
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1 S. Tanoi, Y. Tokunaga, T. Tanabe, K. Takahashi, A. Okada, M. Itoh, Y. Nagatomo, Y. Ohtsuki, M. Uesugi, 'On-Wafer BIST of a 200Gb/s Failed-Bit Search for 1Gb DRAM', ISSCC97, Vol. 40, pp. 70-71, Feb, 1997   DOI
2 Y. Nishimura, M. Hamada, H. Hidaka, H. Ozaki, K. Fujishima, 'A Redundancy Test-Time Reduction Technique in 1-Mbit DRAM with a Multibit test Mode', IEEE JSSC, Vol. 24, No. 1, pp. 43-49, Feb. 1989   DOI   ScienceOn
3 Jeffrey Dreibelbis, John Barth Jr., Rex Kho, Howard Kalter, 'An ASIC Library Granular DRAM Macro with Built-In Self Test', ISSCC98, Vol. 41, pp. 74-75, Feb, 1998   DOI
4 S. Takase, N.Kushiyama, 'A 1.6GB/s DRAM with Flexible Mapping Redundancy Technique and Additonal Refresh Scheme', ISSCC99, Vol. 42, pp. 410-411, Feb, 1999   DOI
5 K. Komatsuzaki, S. Sukegawa, K. Fung, T. Inui, T. Suzuki, R. Rountree, J. You, B. Borchers, T. Komatsuzaki, H. Shichijo, H. Tran, D. Scott, 'Circuit Technique for wide-word I/O path 64MEG DRAM', VLSI Symposium, Japan, May, 1991
6 P. Mazumder, 'Parallel Tes ting of Parametric Fault in a Three Dimensional Dynamic Random-Access Memory', IEEE JSSC, Vol. 23, No. 4, pp. 933-942, Aug., 1988   DOI   ScienceOn
7 S. Mori, H. Miyamoto, Y. Morooka, S. Kikuda, M. Suwa, M. Kinoshita, A. Hachisuka, H. Arima, M. Yamada, T. Yoshihara, S. Kayano, 'A 45ns 64Mb DRAM with a Merged Match-Line Test Architecture,' IEEE J. Solid-State Circuits, vol. 26, pp. 1486-1492, Nov. 1991   DOI   ScienceOn
8 K. Arimoto, K. Fujishima, Y. Matsuda, M. Tsukude, T. Oishi, W. Wakamiya, S. Satoh, M. Yamada, T. Nakano, 'A 60-ns 3.3-V-Only 16-Mbit DRAM with Multipurpose Register,' IEEE JSSC, Vol. 24, pp. 1184-1190, Feb., 1989   DOI   ScienceOn