• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.8
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• pp.1113-1118
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• 2018

Protection in HVDC(High Voltage Direct Current) have the very fast velocity of fault detection. Because Fault in HVDC has the fast propagation, large currents, high interruption cost. The focus to velocity caused possibility of errors like a detection error like a high impedance fault. In this paper, Proposed complex composition for get the reliability and velocity. That used SFCL(Super Conducting Fault Current Limiter), Protection Zone and DTS(Distributed Temperature Sensing). The SFCL was detect the fault by quench and DTS&Protection Zone were perceive the detect by variation too. To examine the proposed method, PSCAD/EMTDC simulated. The results of simulation, proposed methods could the detect of fault to whole HVDC line. And that improved the reliability of fault clearing.

• Journal of Korean Society of Steel Construction
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• v.8 no.3 s.28
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• pp.97-105
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• 1996

A Stochastic line source model is developed to simulate the seismic wave field generated during the rupture propagation process along a fault plane of which length is much larger than its width. The fault plane is assumed to consist of randomly distributed slip zones and barriers and each slip zone is modeled as a point source. By combining the newly developed source model with wave propagation analysis method in a layered 3-D visco-elastic half space, synthetic seismograms are obtained. The calculated accelerograms due to vertical dip slip and strike slip line sources are presented.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.283-286
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• 1996

This study suggests a new methodology for the fault diagnosis based on the signed digraph in developing the fault diagnosis system of a boiler plant. The suggested methodology uses the new model, fault-effect tree. The SDG has the advantage, which is simple and graphical to represent the causal relationship between process variables, and therefore is easy to understand. However, it cannot handle the broken path cases arisen from data uncertainty as it assumes consistent path. The FET is based on the SDG to utilize the advantages of the SDG, and also covers the above problem. The proposed FET model is constructed by clustering of measured variables, decomposing knowledge base and searching the fault propagation path from the possible faults. The search is performed automatically. The fault diagnosis system for a boiler plant, ENDS was constructed using the expert system shell G2 and the advantages of the presented method were confirmed through case studies.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.808-810
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• 1996

In this paper, neural network, which has learning capability, is used for fault type classification and fault section estimation for high speed relaying. The potential of the neural network approach is demonstrated by simulation using ATP. The instantaneous values of voltages and currents are used the inputs of neural networks. This approach determines the fault section directly. In this paper, back-propagation network(BPN) is used for fault type classification and fault section estimation and can use for high speed relaying because it determines fault section within a few msec.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.24-26
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• 1995

In this paper, we investigated transient fault currents in a magnetic coupling High-Tc superconducting current limiter(HCL). It has an important effect on the reliability and stability of the power system. In order to analyze transient fault characteristics of HCL, we fabricated a magnetic coupling HCL and tested it in different fault conditions. An important parameter of design and manufacture which makes HCL inherently reliable is reduction of inrush fault currents. Without inrush fault currents, the currents flowing under such conditions can be limited to a desired-value within one cycle. Inrush fault current depends on saturation, normal spot propagation velocity, turns ratio and the fault angle.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1752-1757
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• 2012

With the development in industry, power demand has increased rapidly. As consumption of power has increased, Demand for new power line and electric capacity has risen. However, in the event of fault, problems occur in extending the range of fault coverage and increasing fault current. In these reasons, protection devise is recognized as the prevention of an accident and fault current. This paper dealt with minimizing fault propagation and limiting fault current by adjusting fault current limiter (FCL) with fast interrupter. At this point, we compared and analyzed characteristics between non-inductive resistance and fault current which is limited by superconducting units. In normal state of the power system, power was supplied to the load, but when fault occurred, the interrupter was operated as CT which detected the over-current. Its operation made the limitation of fault current through a FCL. We concluded that the limiter using superconducting units was more efficient with the increase of power voltage. Superconducting fault current limiter with the fast interrupter prevented the spread of a fault, and improved reliability of power system.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.167-174
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• 1996

In this paper, a fault location algorithm is presented, which uses novel signal processing techniques and takes a new paradigm to overcome some drawbacks of the conventional methods. This new method for fault location on electric power transmission lines uses only one-terminal fault signals. The main feature of the method is hat it uses the high frequency components in fault signal and considers the influence of the source network by using a traveling wave propagation characteristics. As a result, we can develop a high speed, good accuracy fault locator.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.131-134
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• 1990

A back-propagation neural network based system for a fault diagnosis of a chemical process is developed. Training data are acquired from FCD(Fault-Consequence Digraph) model. To improve the resolution of a diagnosis, the system is decomposed into 6 subsystems and the training data are composed of 0, 1 and intermediate values. The feasibility of this approach is tested through case studies in a real plant, a naphtha furnace, which has been used to develop a knowledge based expert system, OASYS (Operation Aiding expert SYStem).