• Journal of KIISE:Software and Applications
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• v.26 no.2
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• pp.223-233
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• 1999

데이터베이스 공유 시스템(Database Sharing System : DSS) 은 고성능의 트랜잭션 처리를 위해 제안된 구조이다. DSS에서 고속의 통신망으로 연결된 노드들은 별도의 메모리와 운영체제, 그리고 DBMS를 가지며, 데이터베이스르 저장하고 있는 디스크는 모든 노드에 의해 공유된다. 빈번한 디스크 액세스를 피하기 위해 각 노드는 자신의 메모리 버퍼에 최근에 액세스한 페이지들을 캐싱한다. 본 논문에서는 레코드와 같은 미세 단위의 로킹을 지원하는 DSS에서 데이터베이스를 정확한 상태로 복구할 수 있는 회복 기법인 DRCP(Database Recovery using Cached Pages)를 제안한다. DRCP는 정상적으로 동작하고 있는 다른 노드에 캐싱된 페이지의 내용을 참조하여 회복 작업을 수행함으로써 디스크 액세스 수와 회복 과정에서 필요한 로그 스캔의 범위를 줄일 수 있고 , 그 결과 데이터베이스를 빨라 복구할 수 있다는 장점을 갖는다.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.22 no.1
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• pp.29-37
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• 1992

The temporomandibular joint was evaluated using magnetic resonance imaging using a urface coil in 11 patients having reciprocal clicking or locking and compared with the normal joint in five subjects. Serial multisection 3㎜-thick parasagittal, paracoronal, and axial image on both closing and opening mouth were obtained with a 1.5 Tesla MR system and surface coil using CSMEMP, GRASS, MPGR, powerful extensions of fast imaging that is currently under clinical evaluation. MR images obtained were analized correlating with the theory of internal derangement. The obtained results were as follows: 1. The serial findings of structures in joint were determined on the serially sectioned images of joint with reciprocal clicking or locking by CSMEMP and MPGR on closing mouth. 2. The delta shaped white images of synovial fluid in the glenoid fossa and on the posterior surface of condyle were revealed on the parasagittal images by MPGR on opening mouth as in the normal joints. 3. The white image of joint fluid surrounding meniscus was recognized on the paracoronal image by GRASS on opening mouth as in the normal joints. 4. In joints having temporomandibular dysfunction the smooth image of displaced meniscus was recognized, but otherwise in the normal joints the image of muscle was noted on the paracoronal image sectioned at the anterior portion of condyle by GRASS. 5. The more thickened fascial plane between superior and inferior belly of lateral pterygoid muscle was not recognizable in joints having temporomandibular dysfunction than in the normal joints.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.26 no.4
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• pp.255-262
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• 2013

In this paper, a shape design sensitivity analysis(DSA) method is presented for Mindlin plates using an isogeometric approach. The isogeometric method possesses desirable advantages; the representation of exact geometry and the higher order inter-element continuity, which lead to the fast convergence of solution as well as accurate sensitivity results. Unlike the finite element methods using linear shape functions, the isogeometric method considers the exact normal vector and curvature of the CAD geometry, taking advantages of higher order NURBS basis functions. A selective reduced integration(SRI) technique is incorporated to overcome the difficulty of 'shear locking' phenomenon. This simple technique is surprisingly helpful for the accuracy of the isogeometric shape sensitivity without complicated formulation. Through the numerical examples of plate bending problems, the accuracy of the proposed isogeometric analysis method is compared with that of finite element one. Also, the isogeometric shape sensitivity turns out to be very accurate when compared with finite difference sensitivity.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.2
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• pp.127-137
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• 2011

We have developed a wearable device that can convert sensor data into real-time step counts and activity levels. Sensor data on gait were acquired using a triaxial accelerometer. A test was performed according to a test protocol for different walking speeds, e.g., slow walking, walking, fast walking, slow running, running, and fast running. Each test was carried out for 36 min on a treadmill with the participant wearing a portable gas analyzer (K4B2), an Actical device, and the device developed in this study. The signal vector magnitude (SVM) was used to process the X, Y, and Z values output by the triaxial accelerometer into one representative value. In addition, for accurate step-count detection, we used three algorithms: an heuristic algorithm (HA), the adaptive threshold algorithm (ATA), and the adaptive locking period algorithm (ALPA). A regression equation estimating the energy expenditure (EE) was derived by using data from the accelerometer and information on the participants. The recognition rate of our algorithm was 97.34%, and the performance of the activity conversion algorithm was better than that of the Actical device by 1.61%.

• Journal of Internet Computing and Services
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• v.15 no.4
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• pp.125-133
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• 2014

The column-oriented database storage is a very advanced model for large-volume data analysis systems because of its superior I/O performance. Traditional data storages exploit row-oriented storage where the attributes of a record are placed contiguously in hard disk for fast write operations. However, for search-mostly datawarehouse systems, column-oriented storage has become a more proper model because of its superior read performance. Recently, solid state drive using MLC flash memory is largely recognized as the preferred storage media for high-speed data analysis systems. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major storage components of modern database servers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of column compression and flash operation as compared to RAM memory. In this research, we propose a new scheme called Column-aware Multi-Version Locking (CaMVL) scheme for efficient transaction processing. CaMVL improves transaction performance by using compression lock and multi version reads for efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of CaMVL. Based on the results of the performance evaluation, we conclude that CaMVL scheme outperforms the traditional scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2444-2450
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• 2011

In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.3
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• pp.976-990
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• 2020

The k-means algorithm is widely used in academia and industry due to easy and simple implementation, enabling fast learning for complex datasets. However, k-means struggles to classify datasets without prior knowledge of specific domains. We proposed the repulsive k-means (RK-means) algorithm in a previous study to improve the k-means algorithm, using the repulsive force concept, which allows deleting unnecessary cluster centroids. Accordingly, the RK-means enables to classifying of a dataset without domain knowledge. However, three main problems remain. The RK-means algorithm includes a cluster repulsive force offset, for clusters confined in other clusters, which can cause cluster locking; we were unable to prove RK-means provided optimal convergence in the previous study; and RK-means shown better performance only normalize term and weight. Therefore, this paper proposes the advanced RK-means (ARK-means) algorithm to resolve the RK-means problems. We establish an initialization strategy for deploying cluster centroids and define a metric for the ARK-means algorithm. Finally, we redefine the mass and normalize terms to close to the general dataset. We show ARK-means feasibility experimentally using blob and iris datasets. Experiment results verify the proposed ARK-means algorithm provides better performance than k-means, k'-means, and RK-means.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.286-288
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• 2007

In this paper, the fast locking PLL Frequency Synthesizer with low phase noise in a 0.18um CMOS process is presented. Its main application IS for the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer, which in this paper, is designed based on self-biased techniques and is independent with processing technology when damping factor and bandwidth fixed to most important parameters as operating frequency ratio, broad frequency range, and input phase offset cancellation. The proposed frequecy synthesizer, which is fully-integrated and is in 320M $^{\sim}$ 960MHz of the frequency range with 10MHz of frequency resolution. And its is implemented based on integer-N architecture. Its power consumption is 50mW at 1.8V of supply voltage and core area is $540{\mu}m$ ${\times}$ $450{\mu}m$. The measured phase noises are -117.92dBc/Hz at 10MHz offset, with low settling time less than $3.3{\mu}s$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.987-992
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• 2002

In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.