• 제목/요약/키워드: fast implementation

검색결과 1,097건 처리시간 0.032초

고속하다마드 변환을 이용한 적응 필터의 구현 (Implementation of adaptive filters using fast hadamard transform)

  • 곽대연;박진배;윤태성
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
    • /
    • pp.1379-1382
    • /
    • 1997
  • We introduce a fast implementation of the adaptive transversal filter which uses least-mean-square(LMS) algorithm. The fast Hadamard transform(FHT) is used for the implementation of the filter. By using the proposed filter we can get the significant time reduction in computatioin over the conventional time domain LMS filter at the cost of a little performance. By computer simulation, we show the comparison of the propsed Hadamard-domain filter and the time domain filter in the view of multiplication time, mean-square error and robustness for noise.

  • PDF

A Fast Implementation of JPEG and Its Application to Multimedia Service in Mobile Handset

  • Jeong Gu-Min;Jung Doo-Hee;Na Seung-Won;Lee Yang-Sun
    • 한국멀티미디어학회논문지
    • /
    • 제8권12호
    • /
    • pp.1649-1657
    • /
    • 2005
  • In this paper, a fast implementation of JPEG is discussed and its application to multimedia service is presented for mobile wireless internet. A fast JPEG player is developed based on several fast algorithms for mobile handset. In the color transformation, RCT is adopted instead of ICT for JPEG source. For the most time-consuming DCT part, the binDCT can reduce the decoding time. In upsampling and RGB conversion, the transformation from YCbCr to RGB 16 bit is made at one time. In some parts, assembly language is applied for high-speed. Also, an implementation of multimedia in mobile handset is described using MJPEG (Motion JPEG) and QCELP(Qualcomm Code Excited Linear Prediction Coding). MJPEG and QCELP are used for video and sound, which are synchronized in handset. For the play of MJPEG, the decoder is implemented as a S/W upon the MSM 5500 baseband chip using the fast JPEG decoder. For the play of QCELP, the embedded QCELP player in handset is used. The implemented multimedia player has a fast speed preserving the image quality.

  • PDF

Fast 웹서비스를 위한 Fast XML 인코딩 시스템 구현 (Implementation of the Fast XML Encoding System for Fast Web Services)

  • 최봉규;조태범;정회경
    • 한국정보통신학회논문지
    • /
    • 제11권4호
    • /
    • pp.800-807
    • /
    • 2007
  • 웹서비스는 서로 다른 플랫폼간의 통합을 가능하게 하였으나, 네트워크 환경이나 임베디드 시스템과 같이 상대적으로 느린 통신 매체에 자주 접속하거나 모바일과 같이 자원이 한정적인 소형 기기에서 사용 할 경우 전체 응용프로그램의 성능을 저하시키는 문제가 발생하고 있다. 이에 ITU-T(International Telecommunication Union - Telecommunication)와 ISO(International Organization for Standardization)/ IEC(International Electrotechnical Commission) 에서 공동으로 바이너리 XML 인코딩 표준을 제안하게 되었으며, 현재 진행 중인 바이너리 XML 인코딩 표준으로는 Fast Infoset과 Fast Schema가 있다. 본 논문에서는 웹서비스의 성능 향상을 위해 현재 표준화가 진행 중인 Fast Infoset 알고리즘과 Fast Schema 알고리즘을 도입하여 Fast XML 인코딩 시스템을 구현하였다. 또한, 구현된 Fast XML 인코더를 통하여 개발자나 사용자들이 Fast 웹서비스 시스템을 구축하는데 있어 참고 할 수 있는 테스트 베드를 제공한다.

실내 환경에서 Infrared 카메라를 이용한 실용적 FastSLAM 구현 방법 (A Practical FastSLAM Implementation Method using an Infrared Camera for Indoor Environments)

  • 장헤이롱;이헌철;이범희
    • 로봇학회논문지
    • /
    • 제4권4호
    • /
    • pp.305-311
    • /
    • 2009
  • FastSLAM is a factored solution to SLAM problem using a Rao-Blackwellized particle filter. In this paper, we propose a practical FastSLAM implementation method using an infrared camera for indoor environments. The infrared camera is equipped on a Pioneer3 robot and looks upward direction to the ceiling which has infrared tags with the same height. The infrared tags are detected with theinfrared camera as measurements, and the Nearest Neighbor method is used to solve the unknown data association problem. The global map is successfully built and the robot pose is predicted in real time by the FastSLAM2.0 algorithm. The experiment result shows the accuracy and robustness of the proposed method in practical indoor environment.

  • PDF

A Fast SIFT Implementation Based on Integer Gaussian and Reconfigurable Processor

  • Su, Le Tran;Lee, Jong Soo
    • 한국정보전자통신기술학회논문지
    • /
    • 제2권3호
    • /
    • pp.39-52
    • /
    • 2009
  • Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

  • PDF

Predictive Direct Torque Control Algorithm for Induction Motors and its Digital Implementation

  • Mutschler, Peter;Flach, Erich
    • 전력전자학회:학술대회논문집
    • /
    • 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
    • /
    • pp.1-6
    • /
    • 1998
  • To achieve fast control action, direct control methods should be used. "Direct Mean Torque Control" (DMTC) combines the good dynamic performance of Direct Torque Control (DTC) with the advantages of inherently constant switching frequency and time equidistant control for implementation in a digital signal processor. Since DMTC is a predictive control algorithm, the model and its correction deserves special investigations. This paper proposes a steady-state Kalman filter which is well suited for fast computation.mputation.

  • PDF

TMS320C6670 기반 LTE-A PDSCH 디코더 구현 (Implementation of LTE-A PDSCH Decoder using TMS320C6670)

  • 이광민;안흥섭;최승원
    • 디지털산업정보학회논문지
    • /
    • 제14권4호
    • /
    • pp.79-85
    • /
    • 2018
  • This paper presents an implementation method of Long Term Evolution-Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a general-purpose multicore Digital Signal Processor (DSP), TMS320C6670. Although the DSP provides some useful coprocessors such as turbo decoder, fast Fourier transformer, Viterbi Coprocessor, Bit Rate Coprocessor etc., it is specific to the base station platform implementation not the mobile terminal platform implementation. This paper shows an implementation method of the LTE-A PDSCH decoder using programmable DSP cores as well as the coprocessors of Fast Fourier Transformer and turbo decoder. First, it uses the coprocessor supported by the TMS320C6670, which can be used for PDSCH implementation. Second, we propose a core programming method using DSP optimization method for block diagram of PDSCH that can not use coprocessor. Through the implementation, we have verified a real-time decoding feasibility for the LTE-A downlink physical channel using test vectors which have been generated from LTE-A Reference Measurement Channel (RMC) Waveform R.6.

내부점 선형계획법에서의 최적기저 추출방법의 구현 (On the Implementation of an Optimal Basis Identification Procedure for Interior Point Method)

  • 임성묵;박순달
    • 경영과학
    • /
    • 제17권2호
    • /
    • pp.1-12
    • /
    • 2000
  • In this study, we deals with the implementation of an optimal basis identification procedure for interior point methods. Our implementation is based on Megiddo’s strongly polynomial algorithm applied to Andersen and Ye’s approximate LP construction. Several techniques are explained such as the use of effective indicator for obtaining optimal partition when constructing the approximate LP, the efficient implementation of the problem reduction technique proposed by Andersen, the crashing procedure needed for fast dual phase of Megiddo’s algorithm and the construction of the stable initial basis. By experimental comparison, we show that our implementation is superior to the crossover scheme implementation.

  • PDF

병렬구조를 이용한 증강현실 구현 (Implementation of augmented reality using parallel structure)

  • 박태룡;허훈;곽재창
    • 전기전자학회논문지
    • /
    • 제17권3호
    • /
    • pp.371-377
    • /
    • 2013
  • 본 논문에서는 FAST와 BRIEF 알고리즘을 기반으로 하는 증강현실을 구현하기 위해서 효율적인 병렬 구조를 제안한다. 객체 인식 알고리즘으로 잘 알려진 SURF 알고리즘은 객체인식에 강인하지만 연산 량이 많아 실시간으로 구현하기에 어려운 단점을 가지고 있다. FAST와 BRIEF 알고리즘을 활용하여 객체를 인식하였고, 임베디드 환경에서 성능을 향상하기 위해 기존의 OpenMP 라이브러리를 사용한 병렬구조를 개선하여 속도를 약 70%에서 100%로 향상 시켰다.

프로세서 구조에 따른 DCT 알고리즘의 구현 성능 비교 (Performance Comparison of DCT Algorithm Implementations Based on Hardware Architecture)

  • 이재성;박영철;윤대희
    • 한국통신학회논문지
    • /
    • 제31권6C호
    • /
    • pp.637-644
    • /
    • 2006
  • 본 논문에서는 MPEG 오디오 부호화 과정 중 서브밴드 필터뱅크를 구현하기 위해 사용되는 DCT(Discrete Cosine Transform) 과정에 대해 구현 시스템의 구조에 따른 DCT 알고리즘의 구현 결과와 성능 차이를 분석한다. 고속 DCT 알고리즘은 코사인 계수의 내적을 통해 구하는 직접 구현 방법보다 연산량이 현저하게 적은 것으로 알려져 있지만, 피연산자의 어드레스가 불규칙적이고 출력 데이터를 재정렬하는 과정이 필요하기 때문에 규칙성이 결여되며, 재정렬만을 위한 추가적인 연산이 필요한 경우도 있다. 따라서 DSP와 같이 반복적인 연산을 고속으로 수행하기 위해 최적화된 구조의 하드웨어에서는 알고리즘의 규칙성이 높은 직접 구현 방법에 비해 고속 알고리즘이 불리한 측면이 있으며, 더욱이 유효 자리수를 제한하는 경우, 직접 구현 방법에 비해 더 많은 프로세싱 단계를 거쳐야 하므로 누적 오차가 커진다. 본 논문에서는 알고리즘의 규칙성과 각 프로세서의 연산 방법간의 관계와 유효 자리수에 따른 누적 오차를 분석하고 프로세서의 구조에 따른 고속 알고리즘의 선택 기준을 제시하였다.