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Performance Comparison of DCT Algorithm Implementations Based on Hardware Architecture  

Lee Jae-Seong (연세대학교 전자공학과 디지털신호처리 연구실)
Pack Young-Cheol (연세대학교 컴퓨터정보통신공학부)
Youn Dae-Hee (연세대학교 전자공학과 디지털신호처리 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.31, no.6C, 2006 , pp. 637-644 More about this Journal
Abstract
This paper presents performance and implementation comparisons of standard and fast DCT algorithms that are commonly used for subband filter bank in MPEG audio coders. The comparison is made according to the architectural difference of the implementation hardware. Fast DCT algorithms are known to have much less computational complexity than the standard method that involves computing a vector dot product of cosine coefficient. But, due to structural irregularity, fast DCT algorithms require extra cycles to generate the addresses for operands and to realign interim data. When algorithms are implemented using DSP processors that provide special operations such as single-cycle MAC (multiply-accumulate), zero-overhead nested loop, the standard algorithm is more advantageous than the fast algorithms. Also, in case of the finite-precision processing, the error performance of the standard method is far superior to that of the fast algorithms. In this paper, truncation errors and algorithmic suitability are analyzed and implementation results are provided to support the analysis.
Keywords
DCT; MPEG Audio; DSP;
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