• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.183-190
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• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.931-937
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• 2003

The principle of the superconducting vortex flow transistor (SVFT) is based on control of the Abrikosov vortex flowing along a channel. The induced voltage is controlled by a bias current and a control current, instead of external magnetic field. The device is composed of parallel weak links with a nearby current control line. We explained the process to get an I-V characteristic equation and described the method to induce the external and internal magnetic field by the Biot-Savarts law in this paper. The equation can be used to predict the I-V curves for fabricated device. From the equation we demonstrated that the current-voltage characteristics were changed with input parameters. I-V characteristics were simulated to analyze a SVFT with multi-channel by a computer program.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.5
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.687-691
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• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.419-427
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• 2016

In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.852-855
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• 2012

A DC-DC converter for EEPROM IPs which perfom erasing by the FN (Fowler-Nordheim) tunneling and programming by the band-to-band tunneling is designed in this paper. For the DC-DC converter for EEPROM IPs using a low voltage of $1.5V{\pm}10%$ as the logic voltage, a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD ($=3.1V{\pm}0.1V$) is a regulated voltage by a voltage regulator using an external voltage of 5V. The designed DC-DC converter outputs VPP (=8V) and VNN (=-8V) in the write mode.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.632-635
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• 2007

We have synthesized 4'-nitrobiphenyl-4-carboxylic acid (NBCA) and fabricated the hole-only device consisting of ITO/NBCA SAM/TPD (1500 ${\AA}$)/Al (500 ${\AA}$) and the organic light emitting diodes (OLEDs) consisting of ITO/NBCA SAM/TPD (600 ${\AA}$)/Alq3 (600 ${\AA}$)/Al (600 ${\AA}$). The prepared hole-only device with NBCA exhibited lower driving voltage than the device with 4-nitrobenzoic acid (NBA). OLEDs using NBCA also show high external quantum efficiency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.5
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• pp.41-45
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• 2001

This paper presents an comparative study on the effect of STATCOM and UPFC to power flow analysis of power systems. The effect of STATCOM can be analyzed with PSS/E program which is generally used in power system analysis, while UPFC model for power flow analysis is not provided yet. Thus, UPFC is equivalently represented as a synchronous condenser and load, while the active and reactive power of the specific transmission line and the voltage of the bus is controlled appropriately. This procedure is implemented by IPLAN which is an external macro program of PSS/E. The simulation results show that UPFC is more effective to control the bus voltage than STATCOM, because UPFC can control not only the bus voltage where the parallel inverter is installed but also the active and reactive power flow in the transmission line where the series inverter is installed.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.155-157
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• 2001

This paper presents an comparative study on the effect of SSSC and UPFC to the power system static analysis. SSSC is used to control active power flow in transmission lines by controlling the phase angle of the injected voltage source which is in rectangular to the line current. UPFC is used to control the magnitude and phase of the injected voltage sources which are connected both in series and in parallel with the transmission line to control power flow and bus voltage. To compare the effect of SSSC and UPFC in power system static analysis, the PSS/E simulation program is used. As the FACTS device model such as SSSC and UPFC is not provided in PSS/E yet, an equivalent load model is used. This procedure is implemented by IPLAN which is an external macro program of PSS/E. The simulation results show that UPFC is more effective to improve bus voltage than SSSC in power system static analysis.

• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.214-216
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• 2000

This paper presents an comparative study on the effect of STATCOM and UPFC to the power system static analysis. The effect of STATCOM can be analyzed with PSS/E program which is generally used in power system analysis, while UPFC model for static analysis is not provided yet. Thus, UPFC is equivalently represented as a synchronous condenser and load, while the active and reactive power of the specific transmission line and the voltage of the bus is controlled appropriately. This procedure is implemented by IPLAN which is an external macro program of PSS/E. The simulation results show that UPFC is more effective to control the bus voltage than STATCOM, because UPFC can control not only the bus voltage where the parallel inverter is installed but also the active and reactive power flow in the transmission line where the series inverter is installed.