• Title/Summary/Keyword: external circuit

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Performance Analysis of 30 kVA Super-Conducting Generator under Light Load (30 kVA 초전도 발전기의 소용량 부하 인가시 운전특성 해석)

  • Ha, Kyoung-Duck;Hwang, Don-Ha;Park, Doh-Young;Kim, Yong-Joo
    • Proceedings of the KIEE Conference
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    • 1999.07a
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    • pp.271-273
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    • 1999
  • In this paper 30 kVA Super-Conducting Generator's test and analysis results of OCC and SCC are presented. Also the test and FE analysis results of the generator under 1.2, 2.4, and 3.6[kW] load are described. For FE analysis of the generator's performance, the external circuit is coupled with the FE region. The generator's end winding reactance is obtained based on the design data, actual dimension, preliminary FE analysis, and empirical formulas. The comparison of FE analysis coupled with external circuit to the test results shows a good agreement.

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Short-Circuit Currents arising at a $M_1-P-M_2$ Contacts ($M_1-P-M_2$형 접촉으로 인하여 생기는 단락전류)

  • D C. Lee
    • 전기의세계
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    • v.25 no.1
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    • pp.95-100
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    • 1976
  • The main purpose of this paper is to study on the transient current due to the change of environmental temperature under no external field in the arrangement of M$_{1}$(metal)-P(polyver)-M$_{2}$(metal). The specimer of polymeric insulator sandwiched by two metal electrodes composes a parallel-plate condenser represented by Maxwell-model. The behaviors of short circuit current flowing in M-P-M arrangement are very complex and the analysis of its conduction mechanism appears to be much complicated. In this paper we can suggest that a contact potential difference as an energetic state exists in the thin film specimen both sides of which are contacted by two different metals having different cook functions. Futhermore the contact potential difference appears to be constant through the course of temperature change, however, the dielectric constant and caparitance of the specimen must be temperature dependent. Accordingly the charge difference induced on both sides of electrodes may be a cause for the shory circuited transient current flowing through the external circuit. It is also suggestive that the results of the observation must be considered in cases of insulation design of electrical machines and D.C. cable for high voltage use.

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Fabrication and charateristics of the foot-spa driving circuit using ultrasonic vibrator (초음파 진동자를 이용한 족욕기용 구동회로 제작 및 특성)

  • Jang, Eun-Sung;Kim, Hyeung-Kyu;Lee, Sang-Ho;Yoo, Ju-Hyun;Hwang, Lak-Hoon;Jeong, Hoy-Seung;Chung, Kwang-Hyun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07b
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    • pp.705-709
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    • 2004
  • In this study, the foot-spa driving circuit using ultrasonic vibrator was manufactured The used ultrasonic vibrator was PSN-PMN-PZT ceramic with the radius of $25{\Phi}$ and the thickness of 2, 2.5, 3, 3.5 and 4mm, respectively. Resonent frequency for driving ultrasonic vibrator at the fabricated circuit was generated using the self exciting and the external exciting methods. Fabricated foot-spa showed the best condition at the resonent frequency of 1.130MHz and the ceramic thickness of 2.0mm. That is, when the foot-spa was operated for 360 min. at $0.5\ell$ water, temperature increase of water was $14^{\circ}C$ at the self exciting method and $16^{\circ}C$ at the external exciting methods, respectively.

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New Thyristor Based ESD Protection Devices with High Holding Voltages for On-Chip ESD Protection Circuits

  • Hwang, Suen-Ki;Cheong, Ha-Young
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.2
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    • pp.150-154
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    • 2019
  • In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

Bandgap Voltage Reference Circuit Design Technology Suitable for Driving Large OLED Display Panel (대형 OLED 디스플레이 패널 구동에 적합한 밴드갭 레퍼런스 회로 설계 및 결과)

  • Moon, Jong Il;Cho, Sang Jun;Cho, Eou Sik;Nam, Chul;Kwon, Sang Jik
    • Journal of the Semiconductor & Display Technology
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    • v.17 no.2
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    • pp.53-56
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    • 2018
  • In this paper, a CMOS bandgap voltage reference that is not sensitive to changes in the external environment is presented. Large OLED display panels need high supply voltage. MOSFET devices with high voltage are sensitive to the output voltage due to the channel length modulation effect. The self-cascode circuit was applied to the bandgap reference circuit. Simulation results show that the maximum output voltage change of the basic circuit is 77mV when the supply voltage is changed from 10.5V to 13.5V, but the proposed circuit change is improved to 0.0422mV. The improved circuit has a low temperature coefficient of $9.1ppm/^{\circ}C$ when changing the temperature from $-40^{\circ}C$ to $140^{\circ}C$. Therefore, the proposed circuit can be used as a reference voltage source for circuits that require a high supply voltage.

The Analysis of Current Limiting Performance in a High-$T_c$ Superconductor using Flux-Lock Concepts

  • 임성훈;최효상;김영순;이성룡;한병성
    • Progress in Superconductivity
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    • v.3 no.2
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    • pp.229-234
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    • 2002
  • In this paper, we analyzed the fault current performance in a $high-T_{c}$ superconductor(HTS) which was installed on flux-lock reactor with an external magnetic field coil covering the HTS. In this HTS fault current limiter using flux-lock concepts, the initial limiting current level can be controlled by adjusting the inductance of the coils. Furthermore, the current limiting characteristics of $high-T_{c}$ superconducting FCL can be improved by applying the external magnetic field into the $high-T_{c}$ superconductor. This paper discusses current limiting performance according to the inductance of the coil 1 in two cases with ac magnetic field coil or not and suggests the methods to improve the current limiting factor $P_{limit}$, which is defined as the ratio of the limited current $I_{FCL}$ at the current limiting phase to the prospective short -circuit current $I_{PSC}$.TEX> PSC/.

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Design of a redundancy control circuit for 1T-SRAM repair using electrical fuse programming (전기적 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로 설계)

  • Lee, Jae-Hyung;Jeon, Hwang-Gon;Kim, Kwang-Il;Kim, Ki-Jong;Yu, Yi-Ning;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.8
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    • pp.1877-1886
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    • 2010
  • In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

The Effect of External DC Electric Field on the Atmospheric Corrosion Behaviour of Zinc under a Thin Electrolyte Layer

  • Liang, Qinqin;YanYang, YanYang;Zhang, Junxi;Yuan, Xujie;Chen, Qimeng
    • Corrosion Science and Technology
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    • v.17 no.2
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    • pp.54-59
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    • 2018
  • The effect of external DC electric field on atmospheric corrosion behavior of zinc under a thin electrolyte layer (TEL) was investigated by measuring open circuit potential (OCP), cathodic polarization curve, and electrochemical impedance spectroscopy (EIS). Results of OCP vs. time curves indicated that the application of external DC electric field resulted in a negative shift of OCP of zinc. Results of cathodic polarization curves measurement and EIS measurement showed that the reduction current of oxygen increased while charge transfer resistance ($R_{ct}$) decreased under the external DC electric field. Variation of OCP negative shift, reduction current of oxygen, and $R_{ct}$ increase with increasing of external DC electric field strength as well as the effect of external DC electric field on double-layer structure in the electrode/electrolyte interface and ions distribution in thin electrolyte layer were analyzed. All results showed that the external DC electric field could accelerate the corrosion of zinc under a thin electrolyte layer.

A Study on the Built-in Test Circuit Design for Parallel Testing of CAM(Content Addressable Memory) (CAM(Content Addressable Memory)의 병렬테스팅을 위한 Built-in 테스트회로 설계에 관한 연구)

  • 조현묵;박노경;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.6
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    • pp.1038-1045
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    • 1994
  • In this paper, algorithm and built-in test circuit for testing all PSF(Pattern Sensitive Fault) occuring in CAM(Content Addressable Memory) are proposed. That is, built-in test circuit that uses minimum additional circuit without external equipment is designed. Additional circuit consist`s of parallel comparator, error detector, and modified decoder for parallel testing. Besides, the study on eulerian path for effectiv test pattern is carried out simultaneously. Consequently, using proposed algorithm, we can test all contents of CAM with 325+2b(b:number of bits) operations regardless of number of words. The area occupied by test circuit is about 7.5% of total circuit area.

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