• The Mathematical Education
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• v.58 no.2
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• pp.319-335
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• 2019

In this paper, we examine the effectiveness of calculation according to automation, which is one of Computational Thinking, by coding the conceptual process into Python language, focusing on the concept of divisibility in elementary school textbooks. The educational implications of these considerations are as follows. First, it is possible to make a field of learning that can revise the new mathematical concept through the opportunity to reinterpret the Conceptual Thinking learned in school mathematics from the perspective of Computational Thinking. Second, from the analysis of college students, it can be seen that many students do not have mathematical concepts in terms of efficiency of computation related to the divisibility. This phenomenon is a characteristic of the mathematics curriculum that emphasizes concepts. Therefore, it is necessary to study new mathematical concepts when considering the aspect of utilization. Third, all algorithms related to the concept of divisibility covered in elementary mathematics textbooks can be found to contain the notion of iteration in terms of automation, but little recursive activity can be found. Considering that recursive thinking is frequently used with repetitive thinking in terms of automation (in Computational Thinking), it is necessary to consider low level recursive activities at elementary school. Finally, it is necessary to think about mathematical Conceptual Thinking from the point of view of Computational Thinking, and conversely, to extract mathematical concepts from computer science's Computational Thinking.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• School Mathematics
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• v.5 no.4
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• pp.421-440
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• 2003

It is difficult for the learner to understand completely the ratio concept which forms a basis of proportional reasoning. And proportional reasoning is, on the one hand, the capstone of children's elementary school arithmetic and, the other hand, it is the cornerstone of all that is to follow. But school mathematics has centered on the teachings of algorithm without dealing with its essence and meaning. The purpose of this study is to analyze the essence of ratio concept from multidimensional viewpoint. In addition, this study will show the direction for improvement of ratio concept. For this purpose, I tried to analyze the historical development of ratio concept. Most mathematicians today consider ratio as fraction and, in effect, identify ratios with what mathematicians called the denominations of ratios. But Euclid did not. In line with Euclid's theory, ratio should not have been represented in the same way as fraction, and proportion should not have been represented as equation, but in line with the other's theory they might be. The two theories of ratios were running alongside each other, but the differences between them were not always clearly stated. Ratio can be interpreted as a function of an ordered pair of numbers or magnitude values. A ratio is a numerical expression of how much there is of one quantity in relation to another quantity. So ratio can be interpreted as a binary vector which differentiates between the absolute aspect of a vector -its size- and the comparative aspect-its slope. Analysis on ratio concept shows that its basic structure implies 'proportionality' and it is formalized through transmission from the understanding of the invariance of internal ratio to the understanding of constancy of external ratio. In the study, a fittingness(or comparison) and a covariation were examined as the intuitive origins of proportion and proportional reasoning. These form the basis of the protoquantitative knowledge. The development of sequences of proportional reasoning was examined. The first attempts at quantifying the relationships are usually additive reasoning. Additive reasoning appears as a precursor to proportional reasoning. Preproportions are followed by logical proportions which refer to the understanding of the logical relationships between the four terms of a proportion. Even though developmental psychologists often speak of proportional reasoning as though it were a global ability, other psychologists insist that the evolution of proportional reasoning is characterized by a gradual increase in local competence.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1216-1224
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• 1988

In this paper, it is presented element generation, addition, multiplication and division algorithm over GF ($2^m$) to calculate multiple-valued logic function. The results of addition and multiplication among these algorithms are applied to the current mode CMOS circuits with ROM structure to design of adder and multiplier on GF ($2^m$). Table-lookup and Euclid's algorithm are required the computation in large quentities when multiple-valued logic functions are developed on GF ($2^m$). On the contrary the presented operation algorithms are prefered to the conventional methods since they are processed without relation to increasing degree m in the general purpose computer. Also, the presened logic circuits are suited for the circuit design of the symmetric multiplevalued truth-tables and they can be implemented addition and multiplication on GF ($2^m$) simultaueously.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.107-112
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• 2011

It is very difficult to factorize composite number, $n=pq$ to integer factorization, p and q that is almost similar length of digits. Integer factorization algorithms, for the most part, find ($a,b$) that is congruence of squares ($a^2{\equiv}b^2$ (mod $n$)) with using factoring(factor base, B) and get the result, $p=GCD(a-b,n)$, $q=GCD(a+b,n)$ with taking the greatest common divisor of Euclid based on the formula $a^2-b^2=(a-b)(a+b)$. The efficiency of these algorithms hangs on finding ($a,b$) and deciding factor base, B. This paper proposes a efficient algorithm. The proposed algorithm extracts B from integer factorization with 3 digits prime numbers of $n+1$ and decides f, the combination of B. And then it obtains $x$(this is, $a=fxy$, $\sqrt{n}$ < $a$ < $\sqrt{2n}$) from integer factorization of $n-2$ and gets $y=\frac{a}{fx}$, $y_1$={1,3,7,9}. Our algorithm is much more effective in comparison with the conventional Fermat algorithm that sequentially finds $\sqrt{n}$ < $a$.

• The KIPS Transactions:PartB
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• v.19B no.1
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• pp.1-8
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• 2012

Mosaic is to make a big image by gathering lots of small materials having various colors. With advance of digital imaging techniques, photomosaic techniques using photos are widely used. In this paper, we presents an automatic photomosaic algorithm based on adaptive tiling and block matching. The proposed algorithm is composed of two processes: photo database generation and photomosaic generation. Photo database is a set of photos (or tiles) used for mosaic, where a tile is divided into $4{\times}4$ regions and the average RGB value of each region is the feature of the tile. Photomosaic generation is composed of 4 steps: feature extraction, adaptive tiling, block matching, and intensity adjustment. In feature extraction, the feature of each block is calculated after the image is splitted into the preset size of blocks. In adaptive tiling, the blocks having similar similarities are merged. Then, the blocks are compared with tiles in photo database by comparing euclidean distance as a similarity measure in block matching. Finally, in intensity adjustment, the intensity of the matched tile is replaced as that of the block to increase the similarity between the tile and the block. Also, a tile redundancy minimization scheme of adjacent blocks is applied to enhance the quality of mosaic photos. In comparison with Andrea mosaic software, the proposed algorithm outperforms in quantitative and qualitative analysis.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.157-164
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• 2011

It is very difficult problem to factorize composite number. Integer factorization algorithms, for the most part, find ($a,b$) that is congruence of squares ($a^2{\equiv}b^2$(mode $n$)) with using factoring(factor base, B) and get the result, $p=GCD(a-b,n)$, $q=GCD(a+b,n)$ with taking the greatest common divisor of Euclid based on the formula $a^2-b^2=(a-b)(a+b)$. The efficiency of these algorithms hangs on finding ($a,b$). Fermat's algorithm that is base of congruence of squares finds $a^2-b^2=n$. This paper proposes the method to find $a^2-b^2=kn$, ($k=1,2,{\cdots}$). It is supposed $b_1$=0 or 5 to be surely, and b is a double number. First, the proposed method decides $k$ by getting kn that satisfies $b_1=0$ and $b_1=5$ about $n_2n_1$. Second, it decides $a_2a_1$ that satisfies $a^2-b^2=kn$. Third, it figures out ($a,b$) from $a^2-b^2=kn$ about $a_2a_1$ as deciding $\sqrt{kn}$ < $a$ < $\sqrt{(k+1)n}$ that is in $kn$ < $a^2$ < $(k+1)n$. The proposed algorithm is much more effective in comparison with the conventional Fermat algorithm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.1-14
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• 2010

With the rapid growth of 3D content industry fields, 3D content-based hashing (or hash function) has been required to apply to authentication, trust and retrieval of 3D content. A content hash can be a random variable for compact representation of content. But 3D content-based hashing has been not researched yet, compared with 2D content-based hashing such as image and video. This paper develops a robust 3D content-based hashing based on key-dependent 3D surface feature. The proposed hashing uses the block surface coefficient using shape coordinate of 3D SSD and curvedness for 3D surface feature and generates a binary hash by a permutation key and a random key. Experimental results verified that the proposed hashing has the robustness against geometry and topology attacks and has the uniqueness of hash in each model and key.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.80-85
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• 2003

This paper proposes Galois Field Arithmetic Unit(GFAU) whose structure does addition, multiplication and division in GF(2m). GFAU can execute maximum two additions, or two multiplications, or one addition and one multiplication. The base architecture of this GFAU is a divider based on modified Euclid's algorithm. The divider was modified to enable multiplication and addition, and the modified divider with the control logic became GFAU. The GFAU for GF(2193) was implemented with Verilog HDL with top-down methodology, and it was improved and verified by a cycle-based simulator written in C-language. The verified model was synthesized with Samsung 0.35um, 3.3V CMOS standard cell library, and it operates at 104.7MHz in the worst case of 3.0V, 85$^{\circ}C$, and it has about 25,889 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.