• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.37-42
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• 1999

In this paper, some of main processes for the next generation integrated circuits, such as Cu damascene process using CMP, electron beam lithography, $SiO_2$ CVD and RIE, Ti/Cu-CVD were carried cut and then, two level Cu interconnects were accomplished. In the results of CMP unit processes, a 4,635 ${\AA}$/min of removal rate, a selectivity of Cu : $SiO_2$ of 150:1, a uniformity of 4.0% are obtained under process conditions of a head pressure of 4 PSI, table and head speed of 25rpm, a oscillation distance of 40 mm, and a slurry flow rate of 40 ml/min. Also 0.18 ${\mu}m\;SiO_2$ via-line patterns are fabricated using 1000 ${\mu}C/cm^2$ dose, 6 minute and 30 second development time and 1 minute and 30 second etching time. And finally sub-0.2 ${\mu}$ twolevel metal interconnects using the developed processes were fabricated and the problems of multilevel interconnects are discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.666-670
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• 2013

Recovery method of silicon wafer from defective products generated from manufacturing process of silicon solar cells was studied. The removal effect of the N layer and antireflection coating (ARC) of the waste solar cell were investigated at room temperature ($25^{\circ}C$) by variation of concentration of $H_3PO_4$, $NH_4HF_2$, and concentration and types of chelating agent. Removal efficiency was the best in the conditions; 10 wt% $H_3PO_4$ 2.0 wt% $NH_4HF_2$, 1.5 wt% Hydantoin. Increasing the concentration of $H_3PO_4$, the surface contamination degree was increased and the thickness of the silicon wafe became thicker than the thickness before surface treatment because of re-adsorption on the silicon wafer surface by electrostatic attraction of the fine particles changed to (+). The etching method by mixed solution of $H_3PO_4$-$NH_4HF_2$-chelating agents was expected to be great as an alternative to conventional RCA cleaning methods and as the recycle method of waste solar cells, because all processes are performed at room temperature, the process is simple, and less wastewater, the removal efficiency of the surface of the solar cell was excellent.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.12
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• pp.27-36
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• 2019

The demand for a low dispersion lens with a small refractive index and a high refractive index is increasing, and accordingly, there is an increasing need for a releasable protective film with high heat resistance and abrasion resistance. On the other hand, the optical industry has not yet established a clear standard for the manufacturing process and quality standards for mold-releasing protective films used in aspheric glass lens molding. Optical lens manufacturers treat this technology as proprietary information. In this study, an experiment was conducted regarding the optimization of ion etching, magnetron, and arc current at each source and filter part, and bias voltage in FCVA (filtered cathode vacuum arc)-based Ta-C thin film coatings. This study found that compared to iridium-rhenium alloy thin film sputtering products, the coating conditions were improved by approximately 50%, 20%, and 40% in terms of thickness, hardness, and adhesive strength of the film, respectively. The thin-film coating process proposed in this study is expected to contribute significantly to the development and utilization of glass lenses, which will help enhance the minimum mechanical properties and quality of the mold-release thin film layer required for glass mold surface forming technology.

• Journal of the Korean Society for Heat Treatment
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• v.25 no.1
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• pp.6-13
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• 2012

HVOF thermal spray coating of 80%WC-CoFe powder is one of the most promising candidate for the replacement of the traditional hard chrome plating and hard ceramics coating because of the environmental problem of the very toxic $Cr^{6+}$ known as carcinogen by chrome plating and the brittleness of ceramics coatings. 80%WC-CoFe powder was coated by HVOF thermal spraying for the study of durability improvement of the high speed spindle such as air bearing spindle. The coating procedure was designed by the Taguchi program, including 4 parameters of hydrogen and oxygen flow rates, powder feed rate and spray distance. The surface properties of the 80%WC-CoFe powder coating were investigated roughness, hardness and porosity. The optimal condition for thermal spray has been ensured by the relationship between the spary parameters and the hardness of the coatings. The optimal coating process obtained by Taguchi program is the process of oxygen flow rate 34 FRM, hydrogen flow rate 57 FRM, powder feed rate 35 g/min and spray distance 8 inch. The coating cross-sectional structure was observed scanning electron microscope before chemical etching. Estimation of coating porosity was performed using metallugical image analysis. The Friction and wear behaviors of HVOF WC-CoFe coating prepared by OCP are investigated by reciprocating sliding wear test at $25^{\circ}C$ and $450^{\circ}C$. Friction coefficients (FC) of coating decreases as sliding surface temperature increases from $25^{\circ}C$ to $450^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of Sensor Science and Technology
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• v.11 no.3
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• pp.163-170
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• 2002

This paper proposes a $10\;{\mu}m$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and micromachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation ($500^{\circ}C$, 1 hr at $H_2O/O_2$) and rapid thermal oxidation (RTO) process ($1050^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to $10\;{\mu}m$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 2dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about -20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.

• Journal of the Korean Vacuum Society
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• v.15 no.6
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• pp.630-636
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• 2006

Scale down of semiconductor gate pattern will make progress centrally line width into transistor according to the high integration and high density of flash memory semiconductor. Recently, the many researchers are in the process of developing research for using the ONO(oxide-nitride-oxide) technology for the gate pattern give body to line breadth of less 100 nm. Therefore, etch rate and etch profile of the line width detail of less 100 nm affect important factor in a semiconductor process. In case of increasing of the platen power up to 50 W at the ICP etcher, etch rate and PR selectivity showed good result when the platen power of ICP etcher has 100 W. Also, in case of changing of HBr gas flux at the platen power of 100 W, etch rate was decreasing and PR selectivity is increasing. We founded terms that have etch rate 320 nm/min, PR selectivity 3.5:1 and etch slope have vertical in the case of giving the platen power 100 W and HBr gas 35 sccm at the ICP etcher. Also notch was not formed.

• Applied Chemistry for Engineering
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• v.31 no.1
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• pp.43-48
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• 2020

Fe₂O₃ nanoparticles with the mixed structure of cubic and nanorod were synthesized by precipitation, hydrothermal, sol-gel method, etching process and heat treatment. Fe₂O₃/TiO₂ core-shell (CS) of type Fe₂O₃@TiO₂ composite was fabricated on a 20 nm nanolayer of TiO₂ coated on the surface of Fe₂O₃ nanoparticles. Fe₂O₃/TiO₂ yolk-shell (YS) composite was prepared by chemical etching and heat treatment of Fe₂O₃/TiO₂ CS nanoparticles. Physical properties of Fe₂O₃, Fe₂O₃@TiO₂ CS and Fe₂O₃@TiO₂ YS nanoparticles were characterized by FE-SEM, HR-TEM and X-ray diffraction. The solar reflectance, commission internationale de l'Elcairage (CIE) color coordinate and heat shield temperatures of Fe₂O₃, CS and YS type Fe₂O₃@TiO₂ pigments filled with poly acrylate (PA) paints were investigated by UV-Vis-NIR spectrometer and homemade heat shield temperature measuring device. The Fe₂O₃@TiO₂ YS red pigment filled PA composite exhibited excellent near infrared light reflecting performance and also reduced the heat shield temperature of 13 ℃ than that of Fe₂O₃ filled counterparts.