• 반도체디스플레이기술학회지
• /
• 제10권4호
• /
• pp.21-23
• /
• 2011

Uniformity of plasma etching processes critically depends on the wafer temperature and its distribution. The wafer temperature is affected by plasma, chucking force, He back side pressure and the surface temperature of ESC(electrostatic chuck). In this work, 3D mathematical modeling is used to investigate the influence of the geometry of coolant path and the temperature distribution of the ESC surface. The model that has the coolant path with less change of the cross-sectional area and the curvature shows low standard deviation of the ESC surface temperature distribution than the model with the coolant path of the larger surface area and more geometric change.

• 전자공학회논문지A
• /
• 제31A권8호
• /
• pp.53-61
• /
• 1994

Intermetallic dielectric layer was formed by using SiO$_2$/SOG/SiO$_2$ for aluminum based dual-metal interconnection process and its electric characteristics were evaluated. The dielectric layer was in the cost and facility point of view more useful than the insulator that was formed by etch-back process. The planarity by using SOG process was about 40% higher than that of the insulator by the CVD process. When SiO$_2$ films were deposited by the PECVD process the Al hillock formation during the next process was restrained bucause the intermetalic insulator was made at low temperature. The leakage current was 1${\times}10^{7}~1{\times}10^{-8}A/cm^{2}$ at the electric field of 10$^{5}$V/cm and breakdown filed was 4.5${\times}10^{6}~7{\times}10^{6}A/cm$. So we had confirmed that siloxane SOG was very useful for intermetallic layer material.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
• /
• pp.420-423
• /
• 1987

Planarization in multilevel metallization is very important to smooth out topographic undulations by conductors, dielectrics, contacts, and vias. One of methods for planarizing interdielectrics, such as the etchback process of the double layer composed of the photoresist on the interdielectric low temperature oxide was introduced. The step heights of interdielectrics before and after etch-back process was measured by Scanning Electron Microscope, and the degree of planarization was analyzed, comparing the differences of the step heights. In this experiment, the degree of planarization was controlled up to about 0.9.

• Korean Chemical Engineering Research
• /
• 제47권6호
• /
• pp.715-719
• /
• 2009

본 연구에서는 DNA 정보를 상변화 물질의 전기저항 변화특성으로 검출할 수 있는 상변화 전극 기판을 개발하였다. 이를 위해 반도체 공정에서 사용하는 Al을 사용하여 전극 기판을 제작하였다. 하지만 주사전자현미경을 이용하여 Al 전극의 단면 상태를 확인해 본 결과 PETEOS(plasma enhanced tetraethyoxysilane) 내에서 보이드(void)가 발생하여 후속공정인 에치백과 세정공정 분위기에 과도하게 노출되어 심하게 손상되어 전극과 PETEOS 사이에 홀(hole)로 변형된다. 이 문제점을 해결하기 위하여 에치백 및 세정 공정을 진행하지 않으면서 $Ge_2Sb_2Te_5$(GST) 박막의 단차피복성(stepcoverage)을 좋게 할 수 있고, 열역학적으로 GST 박막과의 반응성을 고려했을 때 안정적이면서 비저항이 낮은 TiN 재료를 사용하여 상변화 전극 기판을 제작하였다. 주사전자현미경을 통하여 전극의 단면의 상태를 관찰하였으며 TiN 전극과 GST 박막이 정상적으로 연결되어 있는 것을 확인하였다. 또한 저항측정 장비를 사용하여 TiN 상변화 전극 기판 위에 증착된 GST의 비정질과 결정질의 저항을 측정하였고, GST의 비정질과 결정질저항의 차이는 약 1,000배 정도로 신호를 검출하는데 충분함을 확인하였다.

• 대한전자공학회논문지SD
• /
• 제47권4호
• /
• pp.20-25
• /
• 2010

평판형 rib 도파로의 설계 및 공정기술을 바탕으로 632.8 nm에서 동작하는 집적 마흐젠더 간섭계 센서(Mach-Zehnder interferometric sensor)를 제작하였다. 단일모드와 높은 감도의 두 가지 조건을 고려하여 실리카 계열($SiO_2-SiO_xN_y-SiO_2$) rib 도파로를 설계하였고 박막증착, 사진제판, RIE (Reactive Ion Etching)와 같은 반도체 공정들을 이용해 그 기하학적 구조를 구현하였다. 제작된 rib 도파로의 광출력을 cut-back방법으로 분석한 결과, 약 4.82 dB/cm의 전파손실을 측정하였다. 동시에 크롬 식각방지 층 공정을 도입하여 마흐젠더 간섭계 칩 위에 감지영역(sensing zone)을 형상화할 때 발생하는 코어 층 손상을 방지하였다. 제작된 마흐젠더 간섭계 센서를 이용한 증류수/에탄올 혼합물 굴절률 측정실험을 통해 약 $\pi$/($4.04{\times}10^{-3}$)의 소자 감도(sensitivity)를 최종 확인하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제48권7호
• /
• pp.521-524
• /
• 1999

Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2005년도 춘계학술대회
• /
• pp.102-108
• /
• 2005

We have developed highly stabilized (p-i-n)-type protocrystalline silicon (pc-Si:H) multilayer solar cells. To achieve a high conversion efficiency, we applied a double-layer p-type amorphous silicon-carbon alloy $(p-a-Si_{1-x}C_x:H)$ structure to the pc-Si:H multilayer solar cells. The less pronounced initial short wavelength quantum efficiency variation as a function of bias voltage proves that the double $(p-a-Si_{1-x}C_x:H)$ layer structure successfully reduces recombination at the p/i interface. It was found that a natural hydrogen treatment involving an etch of the defective undiluted p-a-SiC:H window layer before the hydrogen-diluted p-a-SiC:H buffer layer deposition and an improvement of the order in the window layer. Thus, we achieved a highly stabilized efficiency of $9.0\%$ without any back reflector.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제6권3호
• /
• pp.162-168
• /
• 2006

To fabricate nanometer scale InGaAs HEMTs, we have successfully developed various novel nano-patterning techniques, including sidewall-gate process and e-beam resist flowing method. The sidewall-gate process was developed to lessen the final line length, by means of the sequential procedure of dielectric re-deposition and etch-back. The e-beam resist flowing was effective to obtain fine line length, simply by applying thermal excitation to the semiconductor so that the achievable final line could be reduced by the dimension of the laterally migrated e-beam resist profile. Applying these methods to the device fabrication, we were able to succeed in making 30nm $In_{0.7}Ga_{0.3}As$ HEMTs with excellent $f_T$ of 426GHz. Based on nanometer scale InGaAs HEMT technology, several high performance millimeter-wave integrated circuits have been successfully fabricated, including 77GHz MMIC chipsets for automotive radar application.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2009년도 추계학술대회 논문집
• /
• pp.366-366
• /
• 2009

후면접합 태양전지는 상용 태양전지의 수평전류 손실(lateral current loss) 이 없으며, 전면전극에 의해 발생하는 그림자 손실(shading loss) 줄인 고효율 태양전지의 하나이다. 생성된 반송자가 후면에 위치한 전극에서 수집되기 때문에 효율향상을 위해서는 불순물에 의한 재결합을 줄이는 것이 중요하다. 따라서 Gettering 은 높은 소수반송자 수명(life-time)을 가지는 고품위 실리콘 기판은 고효율 실리콘태양전지 제작을 위한 중요 요소 기술이다. 본 연구에서는 n-type c-Si 기판을 이용한 고효율 실리콘 이종접합 태양전지제작을 위해 external gettering 공정을 이용하여 고품위 실리콘 기판을 제작하였다. POC13 doping process 의 온도, 시간을 변화시킴으로써 이에 따른 변화를 관찰하였다. 주사전자현미경(SEM)를 통해 etch pit 을 확인 했으며,Four point probe 를 통해 면저항을 측정, 인(P)의 농도를 계산 하였다. 계산된 면저항을 통해 인(P)의 확산 깊이를 계산하였다. Iodine passivation 된 시편을 Qusi-steady state photoconductance (QSSPC)를 이용하여 소수반송자 수명을 측정함으로써 gettering 에 의한 bulk lifetime 향상 효과를 관찰하였다.

• 한국태양에너지학회:학술대회논문집
• /
• 한국태양에너지학회 2011년도 추계학술발표대회 논문집
• /
• pp.40-44
• /
• 2011

Recent studies in crystalline silicon solar cell fabrication have been focused on high efficiency and low cost. However, the rising of the cost results in additional processes to approach high efficiency. The fabrication process also becomes complicated with additional technologies. In this paper, we studied the selective emitter formation with phosphorous paste to improve the conversion efficiency. Selective emitter formations like two-step diffusion or etch-back method require at least one more step compared in the conventional line since heavily and lightly doped area was needed to form separately.However,one-step diffusion process is the method diffusing heavily and lightly doped area at the same time only with additional screen-printing step. This study lays the foundation for the simple way to form the selective emitter.