• 한국통신학회논문지
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• 제38C권10호
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• pp.852-857
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• 2013

본 논문은 오류 마루 영역에서 우수한 성능을 가지는 비이진 LDPC (low-density parity-check) 부호의 설계 방법을 제안하고 성능을 검증한다. 제안된 설계 방법은 비이진 LDPC 부호의 이진 최소 거리(binary minimum distance)를 최대화하도록 패리티 검사 행렬의 비이진 원소 값들을 결정한다. BPSK (binary phase-shift keying) 변조 방식 하에서 제안된 방법으로 설계된 비이진 LDPC 부호가 오류 마루(error floor) 영역에서 우수한 성능을 가지는 것을 Monte Carlo 시뮬레이션과 중요도 표본 추출(importance sampling) 기법을 사용하여 검증한다.

• Journal of information and communication convergence engineering
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• 제9권5호
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• pp.615-618
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• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2005년도 춘계학술대회
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• pp.160-163
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• 2005

This paper proposes a simple MPPT control scheme of a Current-Control-Loop Error system Based that can be obtains a lot of advantage to compare with another digital control method, P&O and IncCond algorithm, that is applied mostly a PV system. An existent method is needed an expensive processor such as DSP that calculated to change the measure power of a using current and voltage sensor at the once. Therefore, it is applied a small home power generation system that required many expenses. But, a proposed method is easy to solve the cost reduction and power unbalance problems that it is used by control scheme to limit error of a current control of common sensor. This proposed algorithm had verified through a simulation and an experiment on battery charger using PIC that is the microprocessor of a low price.

• 한국공작기계학회논문집
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• 제14권1호
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• pp.108-114
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• 2005

Code V was used to make a plan for collimator lens with aspherical surface in the present study. The acquired optical design data were applied for ultra-precision machining. The optimum properties were determined to find ways to compensate the tool positioning error allowance during the ultra-precision machining. In ultra-precision aspheric machining, figure tolerance corrected by tool positioning error be improved by compensation cycle number.

• 한국기계가공학회지
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• 제3권4호
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• pp.50-55
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• 2004

Because of the development in mold industries, the geometrical form accuracy of the milled surface is getting more and more important. It has been known that the geometrical form accuracy is affected by machine conditions, cutting conditions, tool conditions and tool path and so on. Among them, the tool approaching path causes the change in material removal per tooth at the end of each machining cycle. And, this change generates the geometrical form error around the region where the tool engages the workpiece initially. So, it is impossible to eliminate the geometrical error caused by the tool approaching path. Thus, characteristics of this geometrical error are studied analytically and experimentally to minimize this region.

• Journal of Information Processing Systems
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• 제15권6호
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• pp.1438-1448
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• 2019

We present a new technique, called VED (very effective debugging), for detecting and correcting division by zero errors for all types of .NET application. We use applications written in C# because C# applications are distributed through the internet and its executable format is used extensively. A tool called Immunity Debugger is used to reverse engineer executable code to get binaries of source code. With this technique, we demonstrate integer division by zero errors, the location of the error causing assembly language code, as well as error recovery done according to user preference. This technique can be extended to work for other programming languages in addition to C#. VED can work on different platforms such as Linux. This technique is simple to implement and economical because all the software used here are open source. Our aims are to simplify the maintenance process and to reduce the cost of the software development life cycle.

• 전기학회논문지
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• 제60권2호
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• 대한의용생체공학회:의공학회지
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• 제30권6호
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• pp.516-520
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• 2009

The purpose of this study is to determine optimal filtering condition and threshold for the detection of gait-cycles for various walkway slopes as well as gait velocities. Ten young healthy subjects with accelerometer system on thigh and ankle walked on a treadmill at 9 conditions (three speeds and three slopes) for 5 minutes. Two direction signals, i.e. anterior-posterior (AP) and superior-inferior (SI) directions, of each sensor (four sensor orientations) were used to detect specific events of gait cycle. Variation of the threshold (from -1G to 1G) and lowpass cutoff frequency (fc) were applied to the event detection and their performance was evaluated according to the error index (EI), which was defined as the combination of the accuracy and false positive rate. Optimal fc and threshold were determined for each slope in terms of the EI. The optimal fc, threshold and their corresponding EI depended much on the walkway slope so that their coefficients of variation (CV) ranged 19~120%. When all data for 3 slopes were used in the identification of optimal conditions for each sensor, the best error indices for all sensor orientations were comparable ranging 1.43~1.76%, but the optimal fc and threshold depended much on the sensor position. The result indicates that the gait-cycle detection robust to walkway slope is possible by threshold method with well-defined filtering condition and threshold.

• 대한교통학회지
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• 제24권4호
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• pp.117-127
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• 2006

국내외 각급 도시에서 시행중인 실시간 버스정보시스템(BIS)에 있어 버스도착예정시간 정보의 정확도는 시스템에 대한 가치평가의 가장 중요한 요소 중 하나이다. FTMS나 RTMS에서의 VMS정보와는 달리 개별버스의 도착예정시간 정보의 경우는, 가공 및 제공주기 그리고 시스템의 가공과정에서 불가피한 오차가 발생한다. 이를 '시스템 오차'라 규정하고 이들 오차의 평균값을 통계적 기법으로 도출하여, 버스도착예정시간 정보에 보정하는 방안을 제시하였다. 또한 검증을 위해 'A'시의 버스정보시스템에 동 기법에 따라 보정을 수행한 결과, 보정전보다 오차율이 23%감소한 것으로 나타났다. 이처럼 버스도착예정시간 정보의 정확도의 제고를 위해서는 시스템오차를 낮추는 방안이 적용해야 하는데 특히, 위치정보수집 빈도를 높이고, GPS 음영지역 해소 등 분산 값에 영향을 미치는 결측을 줄이기 위한 노력을 강구해야 한다.