• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.10
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• pp.852-857
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• 2013

In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.615-618
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• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.160-163
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• 2005

This paper proposes a simple MPPT control scheme of a Current-Control-Loop Error system Based that can be obtains a lot of advantage to compare with another digital control method, P&O and IncCond algorithm, that is applied mostly a PV system. An existent method is needed an expensive processor such as DSP that calculated to change the measure power of a using current and voltage sensor at the once. Therefore, it is applied a small home power generation system that required many expenses. But, a proposed method is easy to solve the cost reduction and power unbalance problems that it is used by control scheme to limit error of a current control of common sensor. This proposed algorithm had verified through a simulation and an experiment on battery charger using PIC that is the microprocessor of a low price.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.14 no.1
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• pp.108-114
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• 2005

Code V was used to make a plan for collimator lens with aspherical surface in the present study. The acquired optical design data were applied for ultra-precision machining. The optimum properties were determined to find ways to compensate the tool positioning error allowance during the ultra-precision machining. In ultra-precision aspheric machining, figure tolerance corrected by tool positioning error be improved by compensation cycle number.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.3 no.4
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• pp.50-55
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• 2004

Because of the development in mold industries, the geometrical form accuracy of the milled surface is getting more and more important. It has been known that the geometrical form accuracy is affected by machine conditions, cutting conditions, tool conditions and tool path and so on. Among them, the tool approaching path causes the change in material removal per tooth at the end of each machining cycle. And, this change generates the geometrical form error around the region where the tool engages the workpiece initially. So, it is impossible to eliminate the geometrical error caused by the tool approaching path. Thus, characteristics of this geometrical error are studied analytically and experimentally to minimize this region.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1438-1448
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• 2019

We present a new technique, called VED (very effective debugging), for detecting and correcting division by zero errors for all types of .NET application. We use applications written in C# because C# applications are distributed through the internet and its executable format is used extensively. A tool called Immunity Debugger is used to reverse engineer executable code to get binaries of source code. With this technique, we demonstrate integer division by zero errors, the location of the error causing assembly language code, as well as error recovery done according to user preference. This technique can be extended to work for other programming languages in addition to C#. VED can work on different platforms such as Linux. This technique is simple to implement and economical because all the software used here are open source. Our aims are to simplify the maintenance process and to reduce the cost of the software development life cycle.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• Journal of Biomedical Engineering Research
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• v.30 no.6
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• pp.516-520
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• 2009

The purpose of this study is to determine optimal filtering condition and threshold for the detection of gait-cycles for various walkway slopes as well as gait velocities. Ten young healthy subjects with accelerometer system on thigh and ankle walked on a treadmill at 9 conditions (three speeds and three slopes) for 5 minutes. Two direction signals, i.e. anterior-posterior (AP) and superior-inferior (SI) directions, of each sensor (four sensor orientations) were used to detect specific events of gait cycle. Variation of the threshold (from -1G to 1G) and lowpass cutoff frequency (fc) were applied to the event detection and their performance was evaluated according to the error index (EI), which was defined as the combination of the accuracy and false positive rate. Optimal fc and threshold were determined for each slope in terms of the EI. The optimal fc, threshold and their corresponding EI depended much on the walkway slope so that their coefficients of variation (CV) ranged 19~120%. When all data for 3 slopes were used in the identification of optimal conditions for each sensor, the best error indices for all sensor orientations were comparable ranging 1.43~1.76%, but the optimal fc and threshold depended much on the sensor position. The result indicates that the gait-cycle detection robust to walkway slope is possible by threshold method with well-defined filtering condition and threshold.

• Journal of Korean Society of Transportation
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• v.24 no.4 s.90
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• pp.117-127
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• 2006

Many large cities in Korea have implemented or planed to implement a bus information system(BIS) to improve service quality for bus Passengers, mainly by Providing bus arrival time at bus stations. In those systems, similar systematic errors to estimate the bus arrival time occur, which are caused by the cycle time to identify each bus location, the information processing time of the center system, and the cycle time to update the bus arrival information on each terminal. This paper investigated each cause sequentially and estimated three expectations related to the above three causes, respectively using the random incidence concept. Through a validation using real data from a BIS in a city in Korea, fairly amount of improvements on the bus arrival time estimation have been observed.