• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.35-39
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• 2011

Error correcting codes with easy variability in code rate and codeword length in addition to powerful error correcting capability are required for present and future mobile multimedia communication systems. And low complexity is also needed for the compact mobile terminals. In general, the irregular random LDPC(low-density parity-check) code is known to have the superior performance among various LDPC codes. But it has inefficiency since the various parity check matrices for various services should be stored for encoding and decoding. The structured LDPC codes which can easily provide various rates and lengths are studied recently. Therefore, the flexibility, memory size, and error performance of various structured LDPC codes are compared and analyzed in this paper. And the most appropriate structured LDPC code is also suggested.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.882-885
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• 2010

In view of the severe energy constraint in sensor networks, it is important to use the error control scheme of the energy efficiently. In this paper, we presented FEC (Forward Error Correcting) codes in terms of their power consumption. One method of FEC is RS (Reed-Solomon) coding, which uses block codes. RS codes work by adding extra redundancy to the data. The encoded data can be stored or transmitted. It could have errors introduced, when the encoded data is recovered. The added redundancy allows a decoder to detect which parts of the received data is corrupted, and corrects them. The number of errors which are able to be corrected by RS code can determine by added redundancy. We could predict the lifetime of RS codes which transmitted at 32 byte a 1 minutes. RS(15, 13), RS(31, 27), RS(63, 57), RS(127,115), and RS(255,239) can keep the days of 138, 132, 126, 111, and 103 respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.1
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• pp.109-117
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• 2013

Polar codes are the first provable error correcting code achieving the symmetric channel capacity in a wide case of binary input discrete memoryless channel(BI-DMC). However, finite length polar codes have an error floor problem with successive-cancellation list(SCL) decoder. From previous works, we can solve this problem by concatenating CRC(Cyclic Redundancy Check) codes. In this paper we propose to make polar codes having extended-minimum distance from original polar codes without outer codes using correlation with generate matrix of polar codes and that of RM(Reed-Muller) codes. And we compare performance of proposed polar codes with that of polar codes concatenating CRC codes.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.2
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• pp.180-184
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• 2009

The memory is very sensitive to the soft error because the integration of the memory increases under low power environment. Error correcting codes (ECCs) are commonly used to protect against the soft errors. This paper proposes a new genetic ECC design method which reduces power consumption. Power is minimized using the degrees of freedom in selecting the parity check matrix of the ECCs. Therefore, the genetic algorithm which has the novel genetic operators tailored for this formulation is employed to solve the non-linear power optimization problem. Experiments are performed with Hamming code and Hsiao code to illustrate the performance of the proposed method.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.37-42
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• 2019

In this paper, we propose a syndrome decoding scheme that can correct two errors for single error correcting Hamming codes within a code length. The decoding scheme proposed in this paper has the advantage of significantly improving the error rate performance compared to the decoder complexity by correcting multiple errors without substantially increasing the decoding complexity. It is suitable for applications in which the energy use of encoder/decoder is extremely limited and the low error rate performance is required, such as IoT communications and molecular communications. In order to verify the improvement of the error rate performance of the Hamming code with the proposed decoding scheme, we performed simulation on Hamming codes with short code length in the AWGN and BPSK modulation environments. As a result, compared with the conventional decoding method, the proposed decoding scheme showed performance improvement of about 1.1 ~ 1.2[dB] regardless of the code length of the Hamming code.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.43-49
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• 2008

In this paper, a method using the Ant Colony Optimization(ACO) is proposed for reducing the power consumption of memory ECC checker circuitry which provide Single-Error Correcting and Double-Error Detecting(SEC-DED). The H-matrix which is used to generate SEC-DED codes is optimized to provide the minimum switching activity with little to no impact on area or delay using the symmetric property and degrees of freedom in constructing H-matrix of Hsiao codes. Experiments demonstrate that the proposed method can provide further reduction of power consumption compared with the previous works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1014-1020
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• 2008

Storage devices such as memories are widely used in various electronic products. They require high-density memory and currently the data has been stored in multi-level format, that results in high error rate. In this paper, we apply error correction schemes that are widely used in communication system to the storage devices for satisfying low bit error rate and high code rate. In A WGN channel with average BER $10^{-5}$ and $5{\times}10^{-6}$, we study error correction schemes for 4-1evel cell to achieve target code rate 0.99 and target BER $10^{-11}$ and $10^{-13}$, respectively. Since block codes may perform better than the concatenated codes for high code rate, and it is important to use less degraded inner code even when many bits are punctured. The performance of concatenated codes using general feedforward systematic convolutional codes are worse than the block code only scheme. The simulation results show that RSC codes must be used as inner codes to achieve good performance of punctured convolutional codes for high code rate.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.198-202
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• 1988

In digital mobile communications received speech data are affected by burst errors as well as random errors. To overcome these errors we propose a bit-selective forward error correction scheme for the speech data which is sub-band coded at 13 kbps and transmitted over a 16 kbps channel. For a few error correcting codes the signal-to-noise ratio of error-corrected speech is obtained and compared through the simulation of mobile communication channels.

• Bulletin of the Korean Mathematical Society
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• v.52 no.3
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• pp.809-823
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• 2015

This paper is devoted to presenting a MacWilliams type identity for m-spotty RT weight enumerators of byte error control codes over finite commutative Frobenius rings, which can be used to determine the error-detecting and error-correcting capabilities of a code. This provides the relation between the m-spotty RT weight enumerator of the code and that of the dual code. We conclude the paper by giving three illustrations of the results.