• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.6
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• pp.2648-2668
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• 2016

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

• Journal of IKEEE
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• v.20 no.4
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• pp.449-453
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• 2016

Failures would occur because of the hostile nature environment in Wireless Sensor Networks (WSNs) which is deployed randomly. Therefore, considering faults in WSNs is essential when we design WSN. This paper classified fault model in the sensor node. Especially, this paper proposed new error correcting code scheme and fault recovery algorithm in the CH(Cluster Head) node. For the range of the small size information (<16), the parity size of the proposed code scheme has the same parity length compared with the Hamming code, and it has a benefit to generate code word very simple way. This is very essential to maintain reliability in WSN with increase power efficiency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.24-28
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• 1985

In this paper, the cyclic product codes which are capable of correcting random erros and burst errors simultaneously have been designed and constructed. First, the procedure for product of two cyclic codes is shown and thin the encoder and decoder system using the (7,4) cyclic Hamming code and the (3,1) cyclic code is implemented. The micro-computer is used for experiment and the system consists of encoder, decoder and interface circuits. The encoder of cyclic product code is implemented by interlacing encoders while the decoder is implemented by cascading decoders that interlace error trapping decoders. In conclusion, cyclic product codas are easily decodable and are capable of correcting four random errors and eight-burst errors. Better performance is obtained with low error rate.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2562-2570
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• 2014

One of the important hints for inferring the function of unknown proteins is the knowledge about protein subcellular localization. Recently, there are considerable researches on the prediction of subcellular localization of proteins which simultaneously exist at multiple subcellular localization. In this paper, label power-set classification is improved for the accurate prediction of multiple subcellular localization. The predicted multi-labels from the label power-set classifier are combined with their prediction probability to give the final result. To find the accurate probability estimates of multi-classes, this paper employs pair-wise comparison and error-correcting output codes frameworks. Prediction experiments on protein subcellular localization show significant performance improvement.

• Nuclear Engineering and Technology
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• v.50 no.8
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• pp.1306-1313
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• 2018

The randomness and incipient nature of certain faults in reactor systems warrant a robust and dynamic detection mechanism. Existing models and methods for fault diagnosis using different mathematical/statistical inferences lack incipient and novel faults detection capability. To this end, we propose a fault diagnosis method that utilizes the flexibility of data-driven Support Vector Machine (SVM) for component-level fault diagnosis. The technique integrates separately-built, separately-trained, specialized SVM modules capable of component-level fault diagnosis into a coherent intelligent system, with each SVM module monitoring sub-units of the reactor coolant system. To evaluate the model, marginal faults selected from the failure mode and effect analysis (FMEA) are simulated in the steam generator and pressure boundary of the Chinese CNP300 PWR (Qinshan I NPP) reactor coolant system, using a best-estimate thermal-hydraulic code, RELAP5/SCDAP Mod4.0. Multiclass SVM model is trained with component level parameters that represent the steady state and selected faults in the components. For optimization purposes, we considered and compared the performances of different multiclass models in MATLAB, using different coding matrices, as well as different kernel functions on the representative data derived from the simulation of Qinshan I NPP. An optimum predictive model - the Error Correcting Output Code (ECOC) with TenaryComplete coding matrix - was obtained from experiments, and utilized to diagnose the incipient faults. Some of the important diagnostic results and heuristic model evaluation methods are presented in this paper.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.10-17
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• 2007

Hierarchical modulation technology which can make the advanced T-DMB(terrestrial-digital multimedia broadcasting) system backward compatible with the conventional T-DMB system and provide high-rate and high-quality services is introduced in this paper. As additional data streams are embedded within the conventional data streams by the hierarchical modulation, the advanced T-DMB system can provide high-quality video service and more broadcasting service channels. In order to guarantee the quality of both the conventional and additional services powerful error correcting scheme is required. The error performance of advanced T-DMB system with hierarchical modulation is investigated and analyzed according to the various error correcting schemes in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.882-885
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• 2010

In view of the severe energy constraint in sensor networks, it is important to use the error control scheme of the energy efficiently. In this paper, we presented FEC (Forward Error Correcting) codes in terms of their power consumption. One method of FEC is RS (Reed-Solomon) coding, which uses block codes. RS codes work by adding extra redundancy to the data. The encoded data can be stored or transmitted. It could have errors introduced, when the encoded data is recovered. The added redundancy allows a decoder to detect which parts of the received data is corrupted, and corrects them. The number of errors which are able to be corrected by RS code can determine by added redundancy. We could predict the lifetime of RS codes which transmitted at 32 byte a 1 minutes. RS(15, 13), RS(31, 27), RS(63, 57), RS(127,115), and RS(255,239) can keep the days of 138, 132, 126, 111, and 103 respectively.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.13-16
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• 2001

In the Dedicated Short Range Communication (DSRC) system channel, a large number of bit errors occur because of Additive White Gaussian Noise (AWGN) and fading. When an image data is transmitted under the condition, reconstructed image quality is significantly degraded. In this paper, as an alternative to the error correcting code and/or automatic repeat request scheme, we propose an error recovery scheme for image data transmission. We first analyze how transmission errors in the DSRC system channel degrade image quality. Then, in order to improve image quality, we propose error resilient and concealment schemes for still image transmission using DCT-based fixed length coding, hamming code, cyclic redundancy check, and interleaver. Finally, we show its performance by an experiment.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.59-62
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• 2004

The performance of turbo code is improved by updating extrinsic information. The bit patterns are categorized by the transition characteristics of extrinsic information in this paper. And the distribution of these patterns is surveyed according to signal-to-noise ratio. Based on the results, the dominant error pattern is determined at high signal-to-noise ratio range. Thus, it is expected to improve the error performance in the error floor region by correcting the dominant error pattern which is found in this paper.