• ETRI Journal
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• 제30권3호
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• 대한전자공학회논문지SD
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• 제38권10호
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• pp.746-753
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• 2001

본 논문에서 구현한 GenBIST는 메모리 테스팅을 위한 정보를 입력으로 받아 테스트용 회로를 VerilogHDL 코드로 자동 생성해 주는 설계 자동화 툴 이다. 상용 툴 들을 포함한 기존의 툴 들은 대부분 메모리 테스트를 위한 알고리즘들을 라이브러리화하고 이를 회로로 생성해주는 방식인데 반해, 본 논문에서 구현한 툴은 사용자가 정의한 알고리즘대로 회로를 생성해 줌으로써 새로운 알고리즘의 적용을 용이하게 하였다. 또한 다중 메모리를 지원할 수 있게 함으로써 메모리 BIST 회로를 공유할 수 있게 하였고 serial interfaceing 기법을 사용함으로써 경계 주사 기법과 함께 사용될 경우 메모리 테스트를 위한 부가적인 핀을 필요로 않는다.

• 정보처리학회논문지D
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• 제13D권4호
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• pp.573-582
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• 2006

소프트웨어를 블랙박스 테스트 하려면 대상 소프트웨어에 적절한 데이터를 주어 실행해 보아야 한다. 효과적인 테스트가 되기 위해서 테스트 케이스의 선택뿐만 아니라 테스트 케이스가 어떻게 표현되었는가가 중요하다. 또한 정적인 테스트 작업에도 테스트를 위한 체크리스트가 어떻게 작성되었는지에 따라 테스트 작업의 효율성이 좌우된다. 이 논문에서는 비효율적이며 문제가 있는 테스트 케이스와 체크 리스트들을 리엔지니어링 하는 방법을 제시하고 이를 실험 하였다. 임베디드 시스템의 일종인 디지털 방송수신 장치에 탑재된 소프트웨어를 대상으로 하여 이미 사용 중인 테스트 케이스의 효율성과 적합성을 따져보고 이를 리엔지니어링 하였다. 리엔지니어링 한 후의 테스트 케이스의 산출물이 테스트 시간과 커버리지 측면에서 얼마나 효과적인지를 살펴보았다. 또한 제품 계열 개념의 소프트웨어를 테스트하기에 적합하도록 테스트 케이스를 재사용 또는 재구조화 하는 방법도 연구하였다.

• The Journal of the Acoustical Society of Korea
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• 제20권1E호
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• 한국콘크리트학회:학술대회논문집
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• 한국콘크리트학회 1996년도 봄 학술발표회 논문집
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• pp.295-299
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• 1996

Intrinsic Fabry-Perot Optical fiber sensors were embedded to tensile side of the 20cm$\times$20cm$\times$150cm cement concrete structures. The sensors were attached to the reinforcing steels and then, the cement concretes were applied. It took 30 days for curing the specimens. After that, the specimens were tested with 4-point bending method by universal testing machine. Strains were measured and recorded by the strain gauges embedded near optical fiber sensors. Output data of fiber sensor showed good linearity to the strain data from the strain gauges up 2000microstrain. The optical fiber sensors showed good response after yielding of structure while embedded metal film strain gauges did not show any response. We also specimens were broken down. In conclusion, the optical fiber sensors can be used as elements of health monitoring systems for cement concrete infra-structures.

• 한국IT서비스학회지
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• 제6권2호
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• pp.153-160
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• 2007

Middleware for mobile devices, embedded middleware, is used for mobile devices, cellular phone and DMB related services. It is essential for middleware providers to provide high quality middleware in conformity with its standard and interoperability on hardware platforms. The standard conformance and interoperability of embedded middleware are the key factors to make service providers succeed in their business. The quality of embedded middleware could be secured when Tests for the standard conformance and interoperability of embedded middleware are performed with well established test framework. In this paper, we describe middleware testing methodology of standard conformance, interoperability and middleware test framework for mobile devices.

• 비파괴검사학회지
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• 제28권6호
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• pp.524-530
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• 2008

The spin valve tunneling magnetoresistance (SV-TMR) sensor performance is analyzed using Stoner-Wohlfarth model for the detection of eddy current signals in nondestructive testing applications. The SV-TMR response in terms of the applied AC magnetic field dominantly generates the second harmonic amplitude in hard axis direction. The second harmonic eddy current signal detection using SV-TMR sensor shows higher performance than that of the coil sensor at lower frequencies. The SV-TMR sensor with high sensitivity gives a good solution to improve the low frequency performance in comparison with the inductive coil sensors. Therefore, the low frequency eddy current techniques based on SV-TMR sensors are specially useful in the detection of hidden defects, and it can be applied to detect the deeply embedded flaws or discontinuities in the conductive materials.

• 한국음향학회지
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• 제18권1호
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• pp.67-71
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• 1999

본 논문에서는 회로의 테스트 시간과 비용을 절감할 수 있는 BIST(Built-In Self Test)기법을 이용하여 메모리 테스트 알고리즘을 칩내에서 수행하는 회로를 설계하였다. 메모리 테스트에 사용되는 MSCAN, Marching, Checkerboard알고리즘을 수행하는 회로를 구현하기 위해 BIST회로에서 요구되는 구조를 파악하고 VHDL을 이용하여 각 블록별로 기술하였다. 그리고 CAD tool을 이용하여 각 블록에 대한 동작을 검증하고 회로합성기로써 각 알고리즘에 대한 BIST 회로를 추출하였다. 추출된 회로는 전체 메모리에 대해 무시할 정도의 오버헤드를 갖는다.

• 전자공학회논문지C
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• 제34C권8호
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• Journal of Information Processing Systems
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• 제15권6호
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• pp.1462-1471
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• 2019

Real-time embedded systems have become pervasive in general industry. They also began to be applied in such domains as avionics, automotive, aerospace, healthcare, and industrial Internet. However, the system failure of such domains could result in catastrophic consequences. Runtime software testing is required in such domains that demands very high accuracy. Traditional runtime software testing based on handwork is very inefficient and time consuming. Hence, test automation methodologies in runtime is demanding. In this paper, we introduce a software testing system that translates a real-time software into a monitorable real-time software. The monitorable real-time software means the software provides the monitoring information in runtime. The monitoring target are time constraints of the input real-time software. We anticipate that our system lessens the burden of runtime software testing.