• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.746-753
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• 2001

GenBIST implemented in this paper is an automatic CAD tool, which can automatically generate circuitry in VerilogHDL code based on user defined information for the memory testing. While most commercial and conventional CAD tools adopt a method in which they make memory-testing algorithms as a library to generate circuitry, our tool can generate circuitry according to the user-defined algorithm, which makes application of various algorithms easier. In addition, memory BIST circuitry can be shared with other memories by supporting embedded memories in our tool. Also, extra pins for the memory testing are not requited when boundary scan technique is combined.

• The KIPS Transactions:PartD
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• v.13D no.4 s.107
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• pp.573-582
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• 2006

Black-box testing needs to prepare fitting test data, execute software, and examine the result. If we test software effectively, not only selecting test cases but also representing test cases are important. In static testing effectiveness of testing activities also depends on how to represent test cases and checklist to validate. This paper suggests a method for finding ineffective critical test cases and reengineering them. An experiment of reengineering digital set-top box software shows the process and results of checking effectiveness and conformance of current test cases and patching test cases. The result shows how much save the test time and improve test coverage by reengineering test cases. Methods of reuse and restructuring test cases are also studied to fit into embedded product-line software.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• Proceedings of the Korea Concrete Institute Conference
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• 1996.04a
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• pp.295-299
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• 1996

Intrinsic Fabry-Perot Optical fiber sensors were embedded to tensile side of the 20cm$\times$20cm$\times$150cm cement concrete structures. The sensors were attached to the reinforcing steels and then, the cement concretes were applied. It took 30 days for curing the specimens. After that, the specimens were tested with 4-point bending method by universal testing machine. Strains were measured and recorded by the strain gauges embedded near optical fiber sensors. Output data of fiber sensor showed good linearity to the strain data from the strain gauges up 2000microstrain. The optical fiber sensors showed good response after yielding of structure while embedded metal film strain gauges did not show any response. We also specimens were broken down. In conclusion, the optical fiber sensors can be used as elements of health monitoring systems for cement concrete infra-structures.

• Journal of Information Technology Services
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• v.6 no.2
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• pp.153-160
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• 2007

Middleware for mobile devices, embedded middleware, is used for mobile devices, cellular phone and DMB related services. It is essential for middleware providers to provide high quality middleware in conformity with its standard and interoperability on hardware platforms. The standard conformance and interoperability of embedded middleware are the key factors to make service providers succeed in their business. The quality of embedded middleware could be secured when Tests for the standard conformance and interoperability of embedded middleware are performed with well established test framework. In this paper, we describe middleware testing methodology of standard conformance, interoperability and middleware test framework for mobile devices.

• Journal of the Korean Society for Nondestructive Testing
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• v.28 no.6
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• pp.524-530
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• 2008

The spin valve tunneling magnetoresistance (SV-TMR) sensor performance is analyzed using Stoner-Wohlfarth model for the detection of eddy current signals in nondestructive testing applications. The SV-TMR response in terms of the applied AC magnetic field dominantly generates the second harmonic amplitude in hard axis direction. The second harmonic eddy current signal detection using SV-TMR sensor shows higher performance than that of the coil sensor at lower frequencies. The SV-TMR sensor with high sensitivity gives a good solution to improve the low frequency performance in comparison with the inductive coil sensors. Therefore, the low frequency eddy current techniques based on SV-TMR sensors are specially useful in the detection of hidden defects, and it can be applied to detect the deeply embedded flaws or discontinuities in the conductive materials.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.67-71
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• 1999

In this paper, we design circuits embedded in memory chip which perform memory testing algorithms using BIST scheme to reduce testing time and cost for testing. In order to implement circuits for MSCAN, Marching and checkerboard test algorithms, which have widely used in memory testing, we survey structure of the BIST circuits and describe each block of BIST circuits by using VHDL. Thereafter, We verify behavior of each VHDL coding block and extract BIST circuits for target testing algorithms by CAD tool for simulation and synthesis. Extracted circuits have very low area overhead.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1462-1471
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• 2019

Real-time embedded systems have become pervasive in general industry. They also began to be applied in such domains as avionics, automotive, aerospace, healthcare, and industrial Internet. However, the system failure of such domains could result in catastrophic consequences. Runtime software testing is required in such domains that demands very high accuracy. Traditional runtime software testing based on handwork is very inefficient and time consuming. Hence, test automation methodologies in runtime is demanding. In this paper, we introduce a software testing system that translates a real-time software into a monitorable real-time software. The monitorable real-time software means the software provides the monitoring information in runtime. The monitoring target are time constraints of the input real-time software. We anticipate that our system lessens the burden of runtime software testing.