• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.299-305
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• 2020

We have developed a scheduler that additionally consider network performance by extending the Kubernetes developed to manage lots of containers in cloud computing nodes. The network delay adapt characteristics of the compute nodes were learned during server operation and the learned results were utilized to develop placement algorithm by considering the existing measurement units, CPU, memory, and volume together, and it was confirmed that the low delay network service was provided through placement algorithm.

• Proceedings of the Korean Reliability Society Conference
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• 2005.06a
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• pp.295-301
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• 2005

It is not easy to apply fault-tolerant techniques which are used in conventional computer systems successfully to the field of embedded computing system directly. In this paper, we study on the way of minimizing hardware and/or software backups for vehicle embedded computing systems. First, we group parts that constitute vehicle embedded systems and next feature subset is determined using the grouping information derived. The possibility of implementing graceful degradation capability in vehicle embedded systems is verified.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.22-34
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• 1999

In this paper, an efficient test algorithm for embedded dual-port memories is presented. The proposed test algorithm can be used to test embedded dual-port memories faster than the conventional multi-port test algorithms and can be used to completely detect stuck-at faults, transition faults and coupling faults which are major target faults in embedded memories. Also, in this work, BIST which performs the proposed memory testing algorithm is designed using Verilog-HDL, and simulation and synthesis for BIST are performed using Cadence Verilog-XL and Synopsys Design-Analyzer. It has been shown that the proposed test algorithm has high efficiency through experiments on various size of embedded memories.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.259-266
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• 2021

Edge Computing enables real-time big data processing by performing computing close to the physical location of the user or data source. However, in an edge computing environment, various situations that affect big data processing performance may occur depending on temporary service requirements or changes of physical resources in the field. In this paper, we proposed a BigCrawler system that dynamically configures the computing module and storage module according to the big data collection status and computing resource usage status in the edge computing environment. And the feature of big data processing workload according to the arrangement of computing module and storage module were analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.57-64
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• 2005

In this paper, we develop the common CAD tool that creates the automatically BIST IP by user settings for the convenient test of embedded memory. Previous tools have defect that when memory model is changed, BIST IP must re-designed depending on memory model because existing tools is limited the widely used algorithms. We develop the tool that is created automatic BIST IP. It applies the algorithm according to the memory model which user requests We usually use the multi-port asynchronous SRAM needless to refresh as the embedded memory. However, This work researches on the dual-port SRAM.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.5
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• pp.267-275
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• 2012

In this paper, we present the model-based autonomic computing framework for a cyber-physical system which provides a self-management and a self-adaptation characteristics. A development process using this framework consists of two phases: a design phase in which a developer models faults, normal status constrains, and goals of the CPS, and an operational phase in which an autonomic computing engine operates monitor-analysis-plan-execute(MAPE) cycle for managed resources of the CPS. We design a hierachical architecture for autonomic computing engines and adopt the Model Reference Adaptive Control(MRAC) as a basic feedback loop model to separate goals and resource management. According to the GroundVehicle example, we demonstrate the effectiveness of the framework.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• Journal of Korea Multimedia Society
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• v.13 no.8
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• pp.1194-1201
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• 2010

Currently embedded system has been widespreadly used in digital Set-top box, mobile phone, USN, etc and the significance of security has been increased due to be necessarily embedded in these all system. In this paper we propose new integrity verification scheme among the main security requirements in target system based on the korea TTA standard, security reference model for embedded operating system, published in december 2006. Moreover the proposed scheme is more effective than the previous scheme, Jung, et al.[2,6].

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.4
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• pp.165-172
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• 2023

Heterogeneous computing is a technology that utilizes different types of processors to perform parallel processing. It maximizes task processing and energy efficiency by leveraging various computing resources such as CPUs, GPUs, and FPGAs. On the other hand, edge computing has developed with IoT and 5G technologies. It is a distributed computing that utilizes computing resources close to clients, thereby offloading the central server. It has evolved to intelligent edge computing combined with artificial intelligence. Intelligent edge computing enables total data processing, such as context awareness, prediction, control, and simple processing for the data collected on the edge. If heterogeneous computing can be successfully applied in the edge, it is expected to maximize job processing efficiency while minimizing dependence on the central server. In this paper, experiments were conducted to verify the feasibility of various parallel programming models on high-end and low-end edge devices by using benchmark applications. We analyzed the performance of five parallel programming models on the Raspberry Pi 4 and Jetson Orin Nano as low-end and high-end devices, respectively. In the experiment, OpenACC showed the best performance on the low-end edge device and OpenSYCL on the high-end device due to the stability and optimization of system libraries.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.73-79
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• 2009

With the advance of VLSI technology, the capacity and density of memories are rapidly growing. In this paper we proposed MRI (Memory built-in self Repair Imagination zone) as reallocation algorithm. All faulty cells of embedded memory are reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.