• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -3
• /
• pp.1980-1983
• /
• 2002

When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method fur estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권6호
• /
• pp.789-796
• /
• 2014

A CMOS photo detection bias quenching circuit is developed to be used with single photon avalanche photodiodes (SPADs) operating in Geiger mode for the detection of weak optical signals. The proposed bias quenching circuits for the performance improvement reduce the circuit size as well as improve the performance of the quenching operation. They are fabricated in a $0.18-{\mu}m$ standard CMOS technology to verify the effectiveness of this technique with the chip area of only $300{\mu}m^2$, which is about 60 % of the previous reported circuit. Two types of proposed circuits with resistive and capacitive load demonstrated improved performance of reduced quenching time. With a commercial APD by HAMAMATSU, the dead time can be adjusted as small as 50 ns.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
• /
• pp.7-10
• /
• 2003

ABS interface IC for automobiles was designed and their electrical properties were investigated. The voltage regulator was designed to operate in the temperature range from $-20^{\circ}\;to\;120^{\circ}C$ for automobile environment. ABS and brake signal were separated using the duty factor of same frequency or different frequencies. UVLO circuit and constant current circuit were applied for the elimination of noise.

• Transactions on Electrical and Electronic Materials
• /
• 제13권3호
• /
• pp.129-135
• /
• 2012

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2014년도 전력전자학술대회 논문집
• /
• pp.93-94
• /
• 2014

Recently, According to increase of power demand, it was increased a demand that switching power supply have characteristic of low-loss and high-efficiency. So increase of using device, the failure rate increases and service life problem arises. Even though normal circuit protection is applied in designing stage, it is often hard to identify the cause of malfunction in certain cases such as fatigued power supply due to over-running, malfunctions of main elements or over heating. This report will cover experimental results with the prototype we made, that monitors the efficiency of switching power supply and that protects a circuit when it drops below the standard value.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
• /
• pp.79-80
• /
• 2005

In this paper, the circuit models of optical to electrical(O/E) characteristics of waveguide photodiode(WGPD) submodule are examined. Test structures of WGPD and WGPD submodule were fabricated and S21 parameter was measured to characterize the O/E conversion property. Valid circuit models were derived by RF circuit simulation and O/E characteristics were modeled to analyze the effects of model parameters on the WGPD submodule performances. Based on the results, it can be concluded that the suggested WGPD submodule model can explain the characteristics of the O/E conversion of WGPD submodule, where the parasitic components originated from ribbon bonding block crucially influence on the performance of WGPD submodule, are able to show more efficient property by making compact bonding structure. We propose an effective WGPD submodule bonding structure and it can ensure the 40Gbps operation of WGPD.

• 한국CDE학회논문집
• /
• 제9권4호
• /
• pp.416-424
• /
• 2004

In this paper, the heat transfer analysis and thermal stress analysis of the PCB(Printed Circuit Board) equipped in electronic Packages are carried out for various may types of chips on the PCB. And two structural PCB models are used in the analyses. The electronic chips on the PCB usually emit heat and this heat generates the thermal stress around the chip. The thermal load due to the heat generation of chips on the PCB may cause the malfunction of the electronic packages such as a monitor. a computer etc. Hence, the PCB should be designed to withstand these thermal loads. In this paper, the heat transfer analysis and thermal stress analysis are executed for the PCB model with pins and the analysis results are compared with the results for the PCB model without pins. The analysis results show that the PCB model without pins is not good for the thermal stress analysis of PCB, even though these two models have similar heat transfer characteristics. The analysis results also show that the highest thermal stress occurs in the pin especially attached to the highest temperature chip, and the PCB constrained to the electronic package on the long side is structurally more stable than other cases. The analyses of the PCB are executed using the finite element analysis code, NISA.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1997년도 하계학술대회 논문집 F
• /
• pp.2072-2074
• /
• 1997

A new low-cost high power factor correction circuit for electronic ballasts is proposed. The proposed circuit provides good power factor correction, low current harmonic distortion and cost-effectiveness. The prototype meets the IEC555-2 requirements satisfactorily with nearly unity power factor.

• 센서학회지
• /
• 제12권1호
• /
• pp.51-56
• /
• 2003

We describe a charge pump circuit using VCO (voltage controlled oscillator) for storing information into local memories in neural networks. The VCO is used for adjusting the output voltage of the charge pump to the reference voltage and for reducing the fluctuation generated by the clocking scheme. The charge pump circuit is simulated by using Hynix 0.35um CMOS process parameters. The proposed charge pump operates properly regardless to the temperature and the supply voltage variation.

• E2M - 전기 전자와 첨단 소재
• /
• 제9권5호
• /
• pp.506-511
• /
• 1996

This paper deals with an inexpensive, simple and fast Langmuir probe sweeping circuit and its application. This sweeper completes a probe trace in a 1 ms order. Futhermore, the circuit drives a maximum probe voltage of $\pm$30V and has a maximum probe current capability of a few amperes. The plasma parameters are successfully determined using the fast Langmuir probe method.