• Transactions of the Korean Society of Mechanical Engineers B
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• v.28 no.7
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• pp.826-833
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• 2004

Cascade impactors are widely used to collect size classified aerosol. A major disadvantage of this instrument is the required long sampling time. Electrical low pressure impactor has been developed to overcome this disadvantage and to achieve real-time measurements on the particle size distribution. The instrument consists primarily of a corona charger, low pressure cascade impactor and multi channel electrometer. We designed and evaluated the performance of a potable 3-stage low pressure impactor using an electrical method. For the calibration of the impactor, monodispersed particles were generated using evaporation-condensation method followed by electrostatic classification using a DMA(Differential Mobility Analyzer). The collection efficiency curves of the stages can be determined by analysing the fraction of particles collected by each stage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.55-57
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• 2017

Amorphous oxide thin film transistors (TFTs) were fabricated with 0.5 wt% silicon doped zinc tin oxide (a-0.5SZTO) thin film deposited by radio frequency (RF) magnetron sputtering. In order to investigate the effect of annealing treatment on the electrical properties of TFTs, a-0.5SZTO thin films were annealed at three different temperatures ($300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 2 hours in a air atmosphere. The structural and electrical properties of a-0.5SZTO TFTs were measured using X-ray diffraction and a semiconductor analyzer. As annealing temperature increased from $300^{\circ}C$ to $500^{\circ}C$, no peak was observed. This provided crystalline properties indicating that the amorphous phase was observed up to $500^{\circ}C$. The electrical properties of a-0.5SZTO TFTs, such as the field effect mobility (${\mu}_{FE}$) of $24.31cm^2/Vs$, on current ($I_{ON}$) of $2.38{\times}10^{-4}A$, and subthreshold swing (S.S) of 0.59 V/decade improved with the thermal annealing treatment. This improvement was mainly due to the increased carrier concentration and decreased structural defects by rearranged atoms. However, when a-0.5SZTO TFTs were annealed at $700^{\circ}C$, a crystalline peak was observed. As a result, electrical properties degraded. ${\mu}_{FE}$ was $0.06cm^2/Vs$, $I_{ON}$ was $5.27{\times}10^{-7}A$, and S.S was 2.09 V/decade. This degradation of electrical properties was mainly due to increased interfacial and bulk trap densities of forming grain boundaries caused by the annealing treatment.

• Korean Journal of Materials Research
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• v.21 no.2
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.28 no.3
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• pp.349-358
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• 2004

A low pressure impactor is an impaction device to separate airborne particles into aerodynamic size classes at low pressure condition. We designed a two-stage low-pressure impactor to classify submicron sized environmental aerosols. Performance evaluation was carried out for stages 1 and 2 by using an electrical method. Monodisperse liquid dioctyl sebacate (DOS) particles were generated using evaporation-condensation process followed by electrostatic classification using a DMA (differential mobility analyzer). The test particles were in the range of 0.08∼0.8$\mu\textrm{m}$. For the evaluation of the impactor we used two electrometers; one was connected to the impaction plate of the impactor and the other was to the Faraday cage used as a backup filter. The effect of polydispersity of test aerosols on the performance was investigated. The results showed that the experimental 50-% cutoff diameters at each impactor's operation pressure were 0.53 and 0.187$\mu\textrm{m}$ for stages 1 and stage 2, respectively. The effects of operation pressure on the cutoff diameter and the steepness of collection efficiency curves were also investigated.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.3
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• pp.326-333
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• 2003

In the measurement using DMA and CPC in series, there is some time delay for particles classified in DMA to detect in CPC. During this time, the DMA time-response changes due to the velocity profile of sampling tube and the diffusion of particles in the volume that exists between the DMA exit and the detector of ultra-fine CPC. This is called mixing effect. In the accelerated measurement methods like the TSI -SMPS, the size distribution is obtained from the correlation between the time-varying electrical potential of the DMA and the corresponding particle concentrations sampled in DMA. If the DMA time -response changes during this delay time, this can cause the error of a size distribution measured by this accelerated technique. The kernel function considering this mixing effect using the residence time distribution is proposed by Russell et al. In this study, we obtained a size distribution using this kernel to compare to the result obtained by the commercial accelerated measurement system, TSI -SMPS for verification and considered the errors that result from the mixing effect with the geometric mean diameters of originally sampled particles, using virtually calculated responses obtained with this kernel as input data.

• Journal of the Korean Electrochemical Society
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• v.8 no.3
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• pp.130-134
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• 2005

To the best knowledge, the formation and characterization of InSb nanowires have not been reported yet in spite of its good characteristics as a III-V compound semiconductor. The nanowire arrays were potentiostatically electrodeposited in a mixing solution of indium chloride, antimony chloride, citric acid, and potassium citrate according to our previous work on the electrodeposition of the stoichiometric InSb films. The electrical properties of nanowire arrays were measured by semiconductor parameter analyzer, and the microstructural analysis of the nanowires was conducted by employing XRD. Our experimental results indicate that the InSb nanowires have a highly preferred orientation of (220) direction and also exhibit electrical characteristics of n-type semiconductors which we, however, similar to semi-metals mainly due to their narrow band-gap and high electron mobility.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.