• Title/Summary/Keyword: dynamic voltage frequency scaling

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ETS: Efficient Task Scheduler for Per-Core DVFS Enabled Multicore Processors

  • Hong, Jeongkyu
    • Journal of information and communication convergence engineering
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    • v.18 no.4
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    • pp.222-229
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    • 2020
  • Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

Low Power Optimization of MPEG-2 AAC with Microscopic Dynamic Voltage Scaling(DVS) (Microscopic Dynamic Voltage Scaling(DVS) 기반 저전력 MPEG-2 AAC 알고리즘 최적화 구현에 관한 연구)

  • Lee, Eun-Seo;Lee, Jae-Sik;Chang, Tae-Gyu
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.428-430
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    • 2006
  • This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

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Low Power Optimization of MPEG-2 AAC with Microscopic Dynamic Voltage Scaling(DVS) (Microscopic Dynamic Voltage Scaling(DVS) 기반 저전력 MPEG-2 AAC 알고리즘 최적화 구현에 관한 연구)

  • Lee, Eun-Seo;Lee, Jae-Sik;Chang, Tae-Gyu
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.55 no.12
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    • pp.544-546
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    • 2006
  • This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

A Novel High-speed CMOS Level-Up/Down Shifter Design for Dynamic-Voltage/Frequency-Scaling Algorithm (Dynamic-Voltage/Frequency-Scaling 알고리즘에서의 다중 인가 전압 조절 시스템 용 High-speed CMOS Level-Up/Down Shifter)

  • Lim Ji-Hoon;Ha Jong-Chan;Wee Jae-Kyung;Moon Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.6 s.348
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    • pp.9-17
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    • 2006
  • We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

A Dynamic Frequency Controlling Technique for Power Management in Existing Commercial Microcontrollers

  • Lueangvilai, Attakorn;Robertson, Christina;Martinez, Christopher J.
    • Journal of Computing Science and Engineering
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    • v.6 no.2
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    • pp.79-88
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    • 2012
  • Power continues to be a driving force in central processing units (CPU) design. Most of the advanced breakthroughs in power have been in a realm that is applicable to workstation CPUs. Advanced power management systems will manage temperature, dynamic voltage scaling and dynamic frequency scaling in a CPU. The use of power management systems for microcontrollers and embedded CPUs has been modest, and mostly focuses on very large scale integration (VLSI) level optimizations compared to system level optimizations. In this paper, a dynamic frequency controlling (DFC) technique is introduced, to lay the foundation of a system level power management system for commercial microcontrollers. The DFC technique allows a commercial microcontroller to have minor modifications on both the hardware and software side, to allow the clock frequency to change to save power; results in this study show a 10% savings. By adding an additional layer of software abstraction at the interrupt level, the microcontroller can operate without having knowledge of the current clock frequency, and this can be accomplished without having to use an embedded operating system.

FPGA Prototype Design of Dynamic Frequency Scaling System for Low Power SoC (저전력 SoC을 위한 동적 주파수 제어 시스템의 FPGA 프로토타입 설계)

  • Jung, Eun-Gu;Marculescu, Diana;Lee, Jeong-Gun
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.11
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    • pp.801-805
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    • 2009
  • Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

Voltage Selection Methodology for DVFS Overhead Minimization (동적 전압 주파수 스케일링 오버헤드 최소화를 위한 전압 선택 방법론)

  • Chang, Jin Kyu;Han, Tae Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.854-857
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    • 2015
  • As the number of devices integrated on system-on-chip(SoC) increases exponentially, energy reduction technology is essential. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. Since it requires complex voltage regulators and PLL circuits, DVFS tends to have significant overheads. In this paper, we propose a new voltage selection algorithm to minimize transition overhead for multiprocessor SoC (MPSoC). Simulation results show that proposed algorithm appears less energy consumption with transition overhead even though maintains performance.

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Dynamic Voltage Scaling Using Average Execution Time in Real Time Systems (실시간 시스템에서 태스크별 평균 실행 시간을 활용한 동적 전압 조절 방법)

  • 방철원;김용석
    • Proceedings of the IEEK Conference
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    • 2003.07d
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    • pp.1379-1382
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    • 2003
  • Recently, mobile embedded systems used widly in various applications. Managing power consumption is becoming a matter of primary concern because those systems use limited power supply. As an approach reduce power consumption, voltage can be scaled down. according to the execution time and deadline. By reducing the supplying voltage to 1/N power consumption can be reduced to 1/N. DPM-S is a well known method for dynamic voltage scaling. In this paper, we enhanced DPM-S by using average execution time aggressively. The frequency of processor is calculated based in average execution time instead of worst case execution time. Simulation results show that our method achieve up to 5% energy savings than DPM-S.

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Dynamic Voltage Scaling Technique Considering Application Characteristics (응용 프로그램 특성을 고려한 동적 전압 조절 기법)

  • Cho, Young-Jin;Chang, Nae-Hyuck
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.96-104
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    • 2009
  • In the real system environments, the performance of the application is not linearly proportional to the clock frequency of the microprocessor, in contrast to the general assumption of conventional dynamic voltage scaling. In this paper, we analytically model the relation between the performance of the application and the clock frequency of the microprocessor, and introduce the energy-optimal scheduling algorithm for a task set with distinct application characteristics. In addition, we present a theorem for the energy-optimal scheduling, which the derivative of the energy consumption with respect to the execution time should be the same for all the tasks. The proposed scheduling algorithm always generates the energy-optimal scaling factor thanks to the theorem for energy-optimal scheduling. We achieved about 7% additional energy reduction in the experiments using synthetic task sets.

On Effective Slack Reclamation in Task Scheduling for Energy Reduction

  • Lee, Young-Choon;Zomaya, Albert Y.
    • Journal of Information Processing Systems
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    • v.5 no.4
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    • pp.175-186
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    • 2009
  • Power consumed by modern computer systems, particularly servers in data centers has almost reached an unacceptable level. However, their energy consumption is often not justifiable when their utilization is considered; that is, they tend to consume more energy than needed for their computing related jobs. Task scheduling in distributed computing systems (DCSs) can play a crucial role in increasing utilization; this will lead to the reduction in energy consumption. In this paper, we address the problem of scheduling precedence-constrained parallel applications in DCSs, and present two energy- conscious scheduling algorithms. Our scheduling algorithms adopt dynamic voltage and frequency scaling (DVFS) to minimize energy consumption. DVFS, as an efficient power management technology, has been increasingly integrated into many recent commodity processors. DVFS enables these processors to operate with different voltage supply levels at the expense of sacrificing clock frequencies. In the context of scheduling, this multiple voltage facility implies that there is a trade-off between the quality of schedules and energy consumption. Our algorithms effectively balance these two performance goals using a novel objective function and its variant, which take into account both goals; this claim is verified by the results obtained from our extensive comparative evaluation study.