• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• Proceedings of the KSRS Conference
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• v.2
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• pp.725-727
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• 2006

The development of GIS and Location-Based Services requires a high-level database that will be able to allow real-time access to moving objects for spatial and temporal operations. MODB.MM is able to meet these requirements quite adequately, providing operations with the abilities of acquiring, storing, and querying large-scale moving objects. It enables a dynamic and diverse query mechanism, including searches by region, trajectory, and temporal location of a large number of moving objects that may change their locations with time variation. Furthermore, MODB.MM is designed to allow for performance upon main memory and the system supports the migration on out-of-date data from main memory to disk. We define the particular query for truncation of moving objects data and design two migration methods so as to operate the main memory moving objects database system and file-based location storage system with.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1023-1043
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• 2010

As main memory get cheaper, it becomes increasingly affordable to load entire index of DBMS and to access the index. Since speed gap between CPU and main memory is growing bigger, many researches to reduce a cost of main memory access are under the progress. As one of those, cache conscious trees can reduce the cost of main memory access. Since cache conscious trees reduce the number of cache miss by compressing data in node, cache conscious trees can reduce the cost of main memory. Existing cache conscious trees use only fixed one compression technique without consideration of properties of data in node. First, this paper proposes the DC-tree that uses various compression techniques and change data layout in a node according to properties of data in order to reduce cache miss. Second, this paper proposes the level of compression locality that describes properties of data in node by formula. Third, this paper proposes Forced Partial Decomposition (FPD) that reduces the nutter of cache miss. DC-trees outperform 1.7X than B+-tree, 1.5X than simple prefix B+-tree, and 1.3X than pkB-tree, in terms of the number of cache misses. Since proposed DC-trees can be adopted in commercial main memory database system, we believe that DC-trees are practical result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.160-160
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• 2003

This paper describes some of the key issues associated with the patterning of metal electrodes of sub-micron (especially at the critical dimension (CD) of 0.15 $\mu\textrm{m}$) dynamic random access memory (DRAM) devices. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 $\mu\textrm{m}$ and thus the storage node electrode with the CD of 0.15 $\mu\textrm{m}$ could not be fabricated using the Pt electrodes. Accordingly, we have proposed novel techniques to surmount the above difficulties. The Ru electrode for the stack-type structure is introduced and alternative schemes based on the introduction of the concave-type structure using Pt or Ru as an electrode material are outlined.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.87-102
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• 1992

This paper presents the development of event-driven system level simulation tool SMPLE(Smpl Extende, an extention fo smpl) and its application to the performance analysis of multiprocessor computer systems. Because of its data structure, it is very difficult to change, expand or add new functions to simulation language smpl implemented by MacDougall. In SMPLE, we change data structure with structure and pointer, add new functions, and enable dynamic memory management. Using new data structure, facilities, and functions added in SMPLE, we simulate job processing of a shared bus multiprocessor system with autonomous hierarchical I/O subsystem. We set system performance contribution of subsystems and units. The impact of disk I/O on system performance is evaluated under vairous conditions of number of processors, processing power, memory access time and disk seek time.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.116-118
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• 2023

자율주행차가 제공하는 새로운 시장과 경쟁력, 인력 및 시간 절약, 교통 체증 문제 해결 등의 장점을 다루고, UN 사이버 보안 법률에 따른 자율주행차의 기술적인 요구사항을 준수해야 한다. 하지만 자율주행차에 대한 기술적인 요구사항을 준수하는 것으로는 모든 사이버 공격에 대해서 막을 수 없다. 자율주행차의 법적 요구사항과 사이버 보안 위협에 대처하는 방법을 다룬다. 특히 RTOS(Real Time OS)와 같은 실시간 시스템에 매우 위험할 수 있는 DRAM(Dynamic Random Access Memory)에 대한 로우해머링 공격 기법에 대해 분석하고 로우해머링에 대한 보안 방법을 제시한다. 그리고 자율 주행 시스템의 안전과 신뢰성을 보장하기 위해 하드웨어 기반 또는 소프트웨어 기반 방어 기술을 소개하고 있다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• Korean Journal of Optics and Photonics
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• v.15 no.1
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• pp.79-85
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• 2004

We report on a transmittance controlled photomask with phase patterns on the back quartz surface. Theoretical analysis for changes in illumination pupil shape with respect to the variation of size and density of backside phase patterns and experimental results for improvement of critical dimension uniformity on a wafer by using the transmittance controlled photomask are presented. As phase patterns for controlling transmittance of the photomask we used etched contact-hole type patterns with 180" rotative phase with respect to the unetched region. It is shown that pattern size on the backside of the photomask must be made as small as possible in order to keep the illumination pupil shape as close as possible to the original pupil shape and to achieve as large an illumination intensity drop as possible at a same pattern density. The distribution of illumination intensity drop suitable for correcting critical dimension error was realized by controlling pattern density of the contact-hole type phase patterns. We applied this transmittance controlled photomask to a critical layer of DRAM (Dynamic Random Access Memory) having a 140nm design rule and could achieve improvement of the critical dimension uniformity value from 24.0 nm to 10.7 nm in 3$\sigma$.TEX>.