• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.51-58
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• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1168-1177
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• 2015

This paper presents a scheme to improve the line current distortion of power factor corrector (PFC) topology at the zero crossing point using a predictive control algorithm in both the continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The line current in single-phase PFC topology is distorted at the zero crossing point of the input AC voltage because of the characteristic of the general proportional integral (PI) current controller. This distortion degrades the line current quality, such as the total harmonic distortion (THD) and the power factor (PF). Given the optimal duty cycle calculated by estimating the next state current in both the CCM and DCM, the proposed predictive control algorithm has a fast dynamic response and accuracy unlike the conventional PI current control method. These advantages of the proposed algorithm lower the line current distortion of PFC topology. The proposed method is verified through PSIM simulations and experimental results with 1.5 kW bridgeless PFC (BLPFC) topology.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.318-320
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• 2003

This paper presents a novel single-stage high frequency resonant DC-DC converter using zero voltage switching with high input power factor. The proposed high frequency resonant converter integrates half-bridge boost rectifier as power factor corrector (PFC) and half-bridge resonant converter into a single stage. The input stage of the half-bridge boost rectifier is working in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a high power factor is achieved naturally. Simulation results through the Pspice have demonstrated the feasibility of the Proposed DC-DC converter. This proposed converter will be able to be practically used as a power supply in various fields as induction heating applications, DC-DC converter etc.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.750-753
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• 2002

A novel single-stage half-bridge high frequency resonant inverter using ZVS(Zero Voltage Switching) with high input power factor suitable for induction heating applications is presented in this paper. The proposed high frequency resonant Inverter integrates half-bridge boost rectifier as power factor corrector(PFC) and half-bridge resonant inverter into a single stage. The input stage of the half-bridge boost rectifier is working in discontinuous conduction mode (DCM) with constant duty cycle and variable switching frequency. Simulation results through the Pspice have demonstrated the feasibility of the proposed inverter. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, DC-DC converter etc.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1196-1198
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• 2002

A novel single-stage half-bridge high frequency resonant inverter using ZVS(Zero Voltage Switching) with high input power factor suitable for induction heating applications is presented in this paper. The proposed high frequency resonant inverter integrates half-bridge boost rectifier as power factor corrector(PFC) and half-bridge resonant inverter into a single stage. The input stage of the half-bridge boost rectifier is working in discontinuous conduction mode (DCM) with constant duty cycle and variable switching frequency. So that a high power factor is achieved naturally. Simulation results through the Pspice have demonstrated the feasibility of the proposed inverter. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, DC-DC converter etc.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.10
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• pp.610-617
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• 2004

This paper presents a novel high frequency generating circuit integrated chopper-inverter using ZVS with high power-factor. The proposed topology is integrated half-bridge boost rectifier as power factor corrector(PFC) and half-bridge high frequency resonant inverter into a single-stage. The input stage of the half-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. Simulation results have demonstrated the feasibility of the proposed high frequency resonant inverter. Characteristics values based on characteristics analysis through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications. fluorescent lamp and DC-DC converter etc.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.2
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• pp.114-122
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• 2004

This paper presents a novel single-stage active-clamp type high frequency resonant inverter. The proposed topology is integrated full-bridge boost rectifier as power factor corrector and active-clamp type high frequency resonant inverter into a single-stage. The input stage of the full-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. By adding additional active-clamp circuit to conventional class-E high frequency resonant inverter, main switch of inverter part operates not only at Zero-Voltage-Switching mode but also reduces the switching voltage stress of main switch. Simulation results have demonstrated the feasibility of the proposed high frequency resonant inverter. Characteristics values based on characteristics estimation through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in the fields of induction heating applications, fluorescent lamp and DC-DC converter etc.