1 |
S. K. Kao and S. I. Liu, "All-Digital Fast-Locked Synchronous Duty-Cycle Corrector," IEEE Trans. on Circuits and Systems, Vol.53, pp. 1363-1367, 2006.
|
2 |
B. Kim, K. Oh, L. Kim, and D. Lee, "A 500MHz DLL with Second Order Duty Cycle Corrector for Low Jitter," IEEECustomIntegratedCircuits Conference, pp. 325-328, 2005.
|
3 |
J. C. Ha, J. H. Lim, Y. J. Kim, W. Y. Jung, J. K. Wee, "Unified all-digital duty cycle and phase correction circuit for QDR I/O interface," IET Electronics Letters, pp. 1300-1301, 2008.
|
4 |
S. Han and J. Kim, "Hybrid duty-cycle corrector circuit with dual feedback loop," IET Electronics Letters, Vo.47, No.24, pp. 1311-1313, 2011.
DOI
ScienceOn
|
5 |
Y. Min, C. Jeong, K. Kim, W. Choi, J. Son, C. Kim, and S. Kim, "A 0.31-1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications," IEEE Trans. on VLSI Systems, Vol. 20, pp. 1524-1528, 2012.
DOI
ScienceOn
|
6 |
S. Han and J. Kim, "A 0.5-2.0 GHz dual-loop SAR-controlled duty-cycle corrector using a mixed search algorithm," Journal of Semiconductor Technology and Science, Vo.13, No.2, pp. 152-156, 2013.
과학기술학회마을
DOI
ScienceOn
|