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http://dx.doi.org/10.9723/jksiis.2013.18.5.051

Design of clock duty-cycle correction circuits for high-speed SoCs  

Han, Sang Woo (홍익대학교 전자정보통신공학과)
Kim, Jong Sun (홍익대학교 전자정보통신공학과)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.18, no.5, 2013 , pp. 51-58 More about this Journal
Abstract
A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.
Keywords
clock duty-cycle corrector; system-on-chip; clocking; duty-cycle amplifier;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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