• Title/Summary/Keyword: dual-threshold

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Polarization Mode Coupling Constants in Solid-State Lasers

  • Park, Jong-Dae;Cho, Chang-Ho
    • The Journal of Natural Sciences
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    • v.17 no.1
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    • pp.31-37
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    • 2006
  • We have found that the polarization mode coupling between the orthogonally linearly polarized dual mode laser results from the anisotropy of dipole moments. Rate equation analysis demonstrated that high anisotropy in dipole moment components can give rise to law intrinsic mode coupling constants while isotropic dipole moment components give high intrinsic mode coupling constant. The populations at active ion sites are shown to self-organize the populations such that laser mode gain is constant adove threshold while the gain contributions from the each site adjust themselves with pump power.

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Enhancement of Off-Axis Viewing Quality with Temporal Dual Gamma Drive in Patterned Vertical Alignment Mode

  • Yang, Young-Chol;Lee, Baek-Woon;Park, Dae-Jin
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.286-289
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    • 2006
  • Temporal dual gamma drive technology employing the 120Hz refresh rate was developed to enhance the off-axis viewing quality in patterned vertical alignment mode. The color shift ${\Delta}u'v'$ from on-axis to off-axis (60 deg.) for pale orange color, (R,G,B) = (196,124,96), was below 0.01, and the power exponent of gamma curve for off-axis viewing angle (60 deg.) was about 1.8, when the gamma curve for on-axis was set with power exponent of 2.4. The off-axis image distortion index was below 0.180 in contrast to the normal case ${\sim}0.23$. To elevate the response speed of liquid crystal in the intra-frame, the voltage below threshold voltage of liquid crystals was used.

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Feasibility Study of Non-volatile Memory Device Structure for Nanometer MOSFET (나노미터 MOSFET비휘발성 메모리 소자 구조의 탐색)

  • Jeong, Ju Young
    • Journal of the Semiconductor & Display Technology
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    • v.14 no.2
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    • pp.41-45
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    • 2015
  • From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

Design of Arithmetic Architecture Considering Leakage Power Minimization (누설 전력 최소화를 고려한 연산 아키텍쳐 설계)

  • 원대건;김태환
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10a
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    • pp.535-537
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    • 2004
  • 최근의 멀티미디어 시스템 설계 (예: 휴대폰, PDA) 경향에서 전력 소모를 줄이는 연구가 매우 긴요한 상황에, 본 연구는 누설 전류(leakage power)를 줄이는 연산 회로 아키텍쳐 합성 기법을 제안한다. 누설 전류를 줄이기 위한 방법으로 본 연구는 Dual threshold Voltage (Dual-V$_{T}$) 기법을 적용한다. 기존의 연구에서는 회로 설계 단계 중 논리나 트랜지스터 수준에서DUal-V$_{T}$를 적용한 방법과는 달리, 보다 상위 단계인 회로의 아키텍쳐 합성 단계에서의 지연시간 제약 조건을 만족하는 범위에서 최소의 누설전류 소모를 위한 합성 기법을 제안한다 따라서, 지연 시간과 누설전류 간의 Trade-Off를 이용하여 설계 조건에 맞는 융통성 있는 설계 결과를 얻을 수 있는 장점을 제공한다. 본 연구는 케리-세이브 가산기 (Carry-Save Adder) 모듈의 생성 과정에 국한된 합성 알고리즘의 적용을 보이고 있지만, 일반적인 연산 모듈을 사용한 아키텍쳐 설계 과정에서도 본 알고리즘을 쉽게 변형, 적용할 수 있다.

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Comparative study of the pulse shape discrimination (PSD) performance of pixelated stilbene and plastic scintillator (EJ-276) arrays for a coded-aperture-based hand-held dual-particle imager

  • Jihwan Boo ;Manhee Jeong
    • Nuclear Engineering and Technology
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    • v.55 no.5
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    • pp.1677-1686
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    • 2023
  • As the demand for the detection of special nuclear materials (SNMs) increases, the use of imaging instruments that can sensitively image both gamma-ray and neutron signatures has become necessary. This study compared the pulse shape discrimination (PSD) performance of gamma/neutron events when employing either a pixelated stilbene or a plastic (EJ-276) scintillator array coupled to a silicon photomultiplier (SiPM) array in a dual-particle imager. The stilbene array allowed a lower energy threshold above which neutron and gamma-ray events can be clearly distinguished. A greater number of events can, therefore, be used when forming both gamma-ray and neutron images, which shortens the time required to acquire the images by nearly seven times.

Air-gap Signal Treatment at rail-joint in Maglev System (자기부상시스템에서 레일 이음매 통과시 공극 처리방법)

  • Sung, H.K.;Jho, J.M.;Lee, J.M.;Bae, D.K.;Kim, B.S.;Kim, D.S.;Shin, B.C.
    • Proceedings of the KIEE Conference
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    • 2006.04b
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    • pp.310-312
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    • 2006
  • Maglev using EMS becomes unstable by unexpected big air-gap disturbance. The main causes of the unexpected air-gap disturbance are step-wise rail joint and large distance between rail splices. For the stable operation of the Maglev, the conventional system uses the threshold method, which selects one gap sensor among two gap sensors installed on the magnet to read the gap between magnet and guide rail. But the threshold method with a wide bandwidth makes the discontinuous air-gap signal at the rail joints because of the offset in air gap sensors and/or the step-wise rail joins. Further more, in the case of the one with a narrow bend-width, it makes Maglev system unstable because of frequent alternation. In this paper, a new method using fuzzy rule to reduce air-gap disturbances proposed to improve the stability of Maglev system. It treats the air-gap signal from dual gap sensors effectively to make continuous signal without air gap disturbance. Simulation and experiment results proved that the proposed scheme was effective to reduce air-gap disturbance from dual gap sensors in rail joints.

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Improved 20Mb/s CMOS Optical Receiver for Digital Audio Interfaces (디지털 오디오 인터페이스용 개선된 20Mb/s CMOS 광수신기)

  • Yoo, Jae-Tack;Kim, Gil-Su
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.3 s.357
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    • pp.6-11
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    • 2007
  • This paper proposes CMOS optical receivers to reduce effective area and pulse width distortion (PWD) in high definition digital audio interfaces. To mitigate effective area and PWD, proposed receivers include a frans-impedance amplifier (TIA) with dual output and a level shifter with threshold convergence, respectively. Proposed circuits are fabricated using $0.25{\mu}m$ CMOS process and measured result demonstrated the effective area of $270\times120{\mu}m^2$ and PWD of ${\pm}3%$ for the receiver with a dual output TIA, and the effective area of $410\times140{\mu}m^2$ and PWD of ${\pm}2%$ for the receiver with a threshold convergence level shifter.

Low-area Dual mode DC-DC Buck Converter with IC Protection Circuit (IC 보호회로를 갖는 저면적 Dual mode DC-DC Buck Converter)

  • Lee, Joo-Young
    • Journal of IKEEE
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    • v.18 no.4
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    • pp.586-592
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    • 2014
  • In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

Development of Land fog Detection Algorithm based on the Optical and Textural Properties of Fog using COMS Data

  • Suh, Myoung-Seok;Lee, Seung-Ju;Kim, So-Hyeong;Han, Ji-Hye;Seo, Eun-Kyoung
    • Korean Journal of Remote Sensing
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    • v.33 no.4
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    • pp.359-375
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    • 2017
  • We developed fog detection algorithm (KNU_FDA) based on the optical and textural properties of fog using satellite (COMS) and ground observation data. The optical properties are dual channel difference (DCD: BT3.7 - BT11) and albedo, and the textural properties are normalized local standard deviation of IR1 and visible channels. Temperature difference between air temperature and BT11 is applied to discriminate the fog from other clouds. Fog detection is performed according to the solar zenith angle of pixel because of the different availability of satellite data: day, night and dawn/dusk. Post-processing is also performed to increase the probability of detection (POD), in particular, at the edge of main fog area. The fog probability is calculated by the weighted sum of threshold tests. The initial threshold and weighting values are optimized using sensitivity tests for the varying threshold values using receiver operating characteristic analysis. The validation results with ground visibility data for the validation cases showed that the performance of KNU_FDA show relatively consistent detection skills but it clearly depends on the fog types and time of day. The average POD and FAR (False Alarm Ratio) for the training and validation cases are ranged from 0.76 to 0.90 and from 0.41 to 0.63, respectively. In general, the performance is relatively good for the fog without high cloud and strong fog but that is significantly decreased for the weak fog. In order to improve the detection skills and stability, optimization of threshold and weighting values are needed through the various training cases.

Replica Technique regarding research for Bit-Line tracking (비트라인 트래킹을 위한 replica 기술에 관한 연구)

  • Oh, Se-Hyeok;Jung, Han-wool;Jung, Seong-Ook
    • Journal of IKEEE
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    • v.20 no.2
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    • pp.167-170
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    • 2016
  • Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.