• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.5
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• pp.366-372
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• 2018

Three-port dual-active bridge (DAB) converter in a DC microgrid was studied due to its high power density and cost-effectiveness. The other advantages of DAB include galvanic isolation and bidirectional power conversion capability using simple control modulation. The three-port DAB converter consists of a three winding transformer and three bridges. The transformer has three phases, which means that the ports are coupled. Thus, the three-port DAB converter causes unwanted power flows when the load connected to each port changes. The basic operational principles of the three-port DAB converter are presented in this study. The decoupling control strategy of the independent port power transfer is presented with a mathematical power model to overcome the unexpected power flow problem. The validity of the proposed analysis and control strategy is verified with PSIM simulation and experiments using a 1-kW prototype power converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.4
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• pp.286-292
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• 2020

This study proposes a power decoupled multi-port dual-active-bridge (DAB) DC-DC converter employing multiple transformers. Conventional multiport DAB DC-DC converters experience a power coupling issue from the use of a single transformer, which essentially requires complex power decoupling control. To solve this issue, a multiport DAB DC-DC converter employing multiple transformers is proposed to decouple output power without additional complex control algorithms. The proposed converter uses multiple transformers that can expand output ports easily. Therefore, transformers and the proposed multi-port DAB converter can be designed simply. In addition, the number of coupling inductors can be reduced in the proposed three-port DAB converter compared with that in conventional multiport DAB converters. The power decoupling characteristics and equivalent circuit of the proposed converter are analyzed using theoretical model approaches. Finally, a 3-kW laboratory prototype is developed to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1015-1026
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• 2018

A family of dual-DC-input (DI) dual-buck inverters (DBIs) is proposed by employing a DI switching cell as the input of traditional DBIs. Three power ports, i.e. a low voltage DC input port, a high voltage DC input port and an AC output port, are provided by the proposed DI-DBIs. A low voltage DC source, whose voltage is lower than the peak amplitude of the AC side voltage, can be directly connected to the DI-DBI. This supplies power to the AC side in single-stage power conversion. When compared with traditional DBI-based two-stage DC/AC power systems, the conversion stages are reduced, and the power rating and power losses of the front-end Boost converter of the DI-DBI are reduced. In addition, five voltage-levels are generated with the help of the two DC input ports, which is a benefit in terms of reducing the voltage stresses and switching losses of switches. The topology derivation method, operation principles, modulation strategy and characteristics of the proposed inverter are analyzed in-depth. Experimental results are provided to verify the effectiveness and feasibility of the proposed DI-DBIs.

• Journal of electromagnetic engineering and science
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• v.17 no.4
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• pp.233-237
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• 2017

In this paper, a dual-band high frequency (HF) and ultra-high frequency (UHF) radio-frequency identification (RFID) tag antenna is presented that operates in the 13.56 MHz band as well as in the 920 MHz band. A spiral coil along the edges of the antenna substrate is designed to handle the HF band, and a novel meander open complementary split ring resonator (MOCSRR) dipole antenna is utilized to generate the UHF band. The dual-band antenna is supported by a single-feeding port for mono-chip RFID applications. The antenna is fabricated using an FR4 substrate to verify theoretical and simulation designs, and it has compact dimensions of $80mm{\times}40mm{\times}0.8mm$. The proposed antenna also has an omnidirectional characteristic with a gain of approximately 1 dBi.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.23-29
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• 2004

In this paper, the asynchronous quasi dual-port SRAM employing a single port structure in SRAM embedded SOC (System On Chip) is proposed. External host can access the internal SRAM freely and the data on internal SRAM can be transferred to an another external circuitry without a synchronous signal of an external host, which operates as an asynchronous dual-port SRRAH The performances of the proposed circuits and control structure are verified through the simulation and we fabricated it using a 0.35um CMOS technology. As the results, the chip shows reduced area about 20% and saved power also 20% than conventional architectures.

• Proceedings of the Safety Management and Science Conference
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• 2000.05a
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• pp.339-349
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• 2000

Inchon Port is the second largest import-export port of Korea, and has the point at issue such as the excessive logistics cost because of the limits of handling capacity and the chronic demurrage. There are few research activities on the analysis and improvement of the whole port operation, because Inchon Port not only has the dual dock system and various facilities but also handles a various kind of cargo. The purpose of this paper is to develop the simulation program as a long-term strategic support tool, considering the dual dock system and the TU(Terminal Operation Company) system executed since March, 1997 in Inchon Port. The basic input parameters such as arrival intervals, cargo tons, service rates are analyzed and the probability density functions for these parameters are estimated. The main mechanism of simulation model is the discrete event-driven simulation and the next-event time advancing. The program is executed based on the knowledge base and database. From the simulation model, it is possible to estimate the demurrage status through analyzing various scenarios and to establish the long-term port strategic plan.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2018.05a
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• pp.59-60
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• 2018

Busan New Port has continued to expand its capacity to handle transshipment cargos exceeding 50 percent of its total volume, but it is considered inefficient because of the work scheduling based on the worker experience. In particular, depending on the transshipment task situation, which often requires an external truck, excessive congestion caused by the vehicle's delay can lead to increased logistics costs and social costs. One way to resolve this issue is to minimize the single transport of the truck and to maximize dual-cycle transport by putting the finished truck into another task. Therefore, we would like to study how to efficiently schedule transportation transshipment cargos between terminals considering dual-cycle.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.31 no.3
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• pp.264-271
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• 1995

This paper presents the data parallel processing method between a PC and a micro-controller. To implement the method a dual port RAM for a real time data processing is used. In general an A/D & D/AC card is used to send or receive the data into or from the external plant and the PC does only the computation of the A/D and the D/A data because the A/D & D/AC card does not have the ability of computation. In this study, a data parallel processing method in which the PC and micro-controller own a common dual port RAM, is introduced, so that the PC can compute the A/D and D/A data and control the plant simultaneously. The PC system with a micro-controller and the common dual port RAM is designed and its effectiveness is investigated experimentally considering the performance of both the computation of data and the controlling and monitoring the external plant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.55-62
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• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.