• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• 전기학회논문지
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• 제67권2호
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• pp.270-276
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• 2018

Apache Spark is one of the high performance in-memory computing frameworks for big-data processing. Recently, to improve the performance, general-purpose computing on graphics processing unit(GPGPU) is adapted to Apache Spark framework. Previous Spark-GPGPU frameworks focus on overcoming the difficulty of an implementation resulting from the difference between the computation environment of GPGPU and Spark framework. In this paper, we propose a Spark framework based on a heterogenous pipeline computing with OpenCL to further improve the performance. The proposed framework overlaps the Java-to-Native memory copies of CPU with CPU-GPU communications(DMA) and GPU kernel computations to hide the CPU idle time. Also, CPU-GPU communication buffers are implemented with switching dual buffers, which reduce the mapped memory region resulting in decreasing memory mapping overhead. Experimental results showed that the proposed Spark framework based on a heterogenous pipeline computing with OpenCL had up to 2.13 times faster than the previous Spark framework using OpenCL.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제5B권2호
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• pp.181-188
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• 2005

In this paper, a DC smoothing filterless soft switching pulse modulated high frequency AC power conversion circuit connected to utility. frequency AC power source is proposed for consumer induction heating hot water producer, steamer and super heated steamer. The operating principle of DC link filterless utility frequency AC-high frequency AC (HF AC) power conversion circuit defined as high frequency cycloinverter is described, which can operate under a principle of ZVS/AVT and power regulation based on alternate asymmetrical PWM in synchronization with the utility frequency single phase AC positive or negative half wave voltage. The dual mode modulation control scheme based on high frequency PWM and commercial frequency AC voltage PDM for the proposed high frequency cycloinverter are discussed to enlarge its soft switching commutation operating range for wide HF AC power regulation. This high frequency cycloinverter is developed for high frequency IH Dual Packs Heater (DPH) type boiler used in consumer and industrial fluid pipeline systems. Based on the experiment and simulation results, this high frequency cycloinverter is proved to be suitable for the consumer use IH-DPH boiler and hot water producers. The cycloinverter power regulation and power conversion efficiency characteristics are evaluated and discussed.

• 전기전자학회논문지
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• 제27권4호
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• pp.683-686
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• 2023

본 논문에서는 차량 전자 시스템에서 소프트 에러와 공통 고장에 대응하기 위해 두 개의 코어를 지연 동작시킨 후 그 결과를 비교하는 D-DCLS(Delayed Dual Core Lock-Step) 프로세서를 설계하였다. D-DCLS는 어느 코어에서 에러가 발생했는지 알 수 없기 때문에 각 코어를 에러가 발생하기 이전 시점으로 되돌려야 하는데 파이프라인 스테이지 상의 모든 중간 계산값을 되돌리기 위해서는 복잡한 하드웨어 수정이 필요하다. 본 논문에서는 이를 쉽게 구현하기 위해 분기 명령어가 실행될 때마다 모든 레지스터 값을 버퍼에 저장해 두었다가 에러가 발생하면 저장된 레지스터 값을 복구한 후 'BX LR' 명령어를 수행하여 해당 분기 시점으로 자동 복구하도록 하였다. 제안하는 D-DCLS 프로세서를 Verilog HDL로 설계하여 에러가 감지되었을 때 자동으로 복구한 후 정상 동작하는 것을 확인하였다.

• 한국재난정보학회 논문집
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• 제12권2호
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• pp.122-129
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• 2016

본 연구에서는 돌발적 충격에 의한 파손사전 예방감시를 위한 이중구조 파이프, 측량 및 시공 속성정보 수집을 위한 스마트 폰 앱 프로그램 개발, 실시간 감시를 위한 서버프로그램 등을 개발하였다. 본 연구에서 개발한 시스템의 효과를 분석하기 위하여 파일럿규모의 시험을 야외시험장에 구축하였다. 파손 예방을 위한 데이터는 파이프에 부착된 센서를 통하여 감지된다. 누출은 압력센서를 일정한 간격으로 설치하여 시험하였다. VRS 측량장비와 스마트폰을 연계한 앱 프로그램과 서버프로그램을 통하여 실시간 자료 수집과 감시가 가능하도록 하였다.

• 한국통신학회논문지
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• 제19권6호
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• pp.1046-1055
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• 1994

본 논문에서는 영상 신호처리에 적합한 고속 1 line VRAM을 ASIC화 설계하기 위하여 엑세스 시간특성 및 집적도가 우수한 3-TR dual-port 다이나믹 셀을 채용하여 메모리 코어를 설계하였다. 고속 파이프라인 동작을 위하여 서브어레이 1로부터 첫 행을 분리하였고, TM기 비트 라인에 데이터 래치 구조를 채용하여 한 번지의 동시 입.출력이 가능하도록 설계하였다. 주변 회로로 번지 선택기, 1/2V 전압 발생기를 각각 설계하여 개선된 동작특성을 확인한 후 1.5[ m] CMOS 설계규칙을 이용하여 ASIC화 설계하였다.

• 전자공학회논문지B
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• 제32B권3호
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• pp.11-23
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• 1995

In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

• 정보와 통신
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• 제25권12호
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2002년도 추계학술대회 논문집
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• pp.129-133
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• 2002

곡선 구간에 복합 해저관로를 설치하기 위해서는 한 개의 관로를 설치하는데 필요한 설계 및 장치보다 더 많은 상황들을 고려해야 한다. 본 논문은 두 개의 복합 해저관로를 설치하는데 필요한 각종 설치 설계 및 장치 설계를 비롯하여 개발된 특수 장치들을 소개한다. 두 개의 해저관로의 외경은 30 inch, 두께는 17.5 mm, 콘크리트 코팅은 70mm이고 3.007km의 노선 중 약 1km가 곡선 구간이다. 최대 수심은 34m이고 약 7.5m의 조수간만의 차를 갖고 있는 지역이다. 해저 곡선구간에는 18개의 해저 가이드 파일을 설치하여 곡선부에서 요구되는 반경을 확보하였다.

• 천문학회보
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• 제44권1호
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• pp.74.1-74.1
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• 2019

We present an ongoing imaging survey of the host galaxies of hard X-ray-selected active galactic nuclei (AGNs) observed with the Hubble Space Telescope (HST). The snapshot images are taken with the Advanced Camera for Surveys through an HST gap-filler program. The sample, selected from the 70-month Swift-BAT X-ray source catalog, represents an unbiased and uniform AGN population, which will enable us to test the AGN unification model and explore the physical connection between host galaxies and central supermassive black holes. We also plan to investigate the AGN triggering mechanism by examining merger signatures and searching for dual nuclei. We present the pipeline for imaging analysis and the current status of the survey.