• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.618-629
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• 2007

In this paper, we propose an effective memory test environment, called a virtualized kernel, for 64bit multi-core computing environments. The term of effectiveness means that we can test all of the physical memory space, even the memory space occupied by the kernel itself, without rebooting. To obtain this capability, our virtualized kernel provides four mechanisms. The first is direct accessing to physical memory both in kernel and user mode, which allows applying various test patterns to any place of physical memory. The second is making kernel virtualized so that we can run two or more kernel image at the different location of physical memory. The third is isolating memory space used by different instances of virtualized kernel. The final is kernel hibernation, which enables the context switch between kernels. We have implemented the proposed virtualized kernel by modifying the latest Linux kernel 2.6.18 running on Intel Xeon system that has two 64bit dual-core CPUs with hyper-threading technology and 2GB main memory. Experimental results have shown that the two instances of virtualized kernel run at the different location of physical memory and the kernel hibernation works well as we have designed. As the results, the every place of physical memory can be tested without rebooting.

• Korean Journal of Adult Nursing
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• v.27 no.6
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• pp.707-717
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• 2015

Purpose: This study was to develop and verify the effects of the exercise-cognitive combined dual-task training program on cognitive function and depression of the elderly with mild cognitive impairment (MCI). Methods: A non-equivalent control group pretest-posttest design was used. The participants were assigned into two groups: an experimental group receiving an exercise-cognitive combined dual-task (n=20) and a control group receiving a simple-task (n=18). After 8 weeks of intervention (2 days per week), the change in depression and cognitive functions were compared between the groups. Results: General cognitive function (t=-2.81, p=.011), frontal cognitive function (Z=-3.50, p<.001), attention/working memory function (U=-2.91, p=.004), depression (t=4.96, p<.001) of the experimental group were significantly increased than those of the control group. Conclusion: The findings of the study showed that an exercise-cognitive combined dual-task program for MCI was effective in improving general cognitive function, frontal and executive function, attention/working memory function, and reducing depression.

• ETRI Journal
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• v.32 no.1
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• pp.84-92
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• 2010

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.4
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• pp.310-318
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• 2015

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1327-1331
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• 1990

A new dual loop controller using color LCD bar graphs with LED back lights has been developed. An optional memory card is used to load or save the controller configuration, which may be a preprogrammed standard package or a user-programmed configuration, in addition to the built-in functions ready for user selection. The bar-graph display is selectable for single-loop or dual-loop use. A high grade of self-tuning functions using a modeling technique is built-in as standard. The controller can accommodate optional plug-in modules for thermocouples, communication, etc. All the options are fully field upgradable.

• Journal of Magnetics
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• v.16 no.4
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• pp.328-331
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• 2011

Here, we describe a dual spin valve structure with distinct switching fields for two pinned layers. A device with this structure has a staircase of three distinct magnetoresistive states. The multiple resistance states are achieved by controlling the exchange coupling between two ferromagnetic pinned layers and two adjacent anti-ferromagnetic pinning layers. The maximum magnetoresistance ratio is 7.9% for the current-perpendicular-to-plane and 7.2% for the current-in-plane geometries, with intermediate magnetoresistance ratios of 3.9% and 3.3%, respectively. The requirements for using this exchange-biased stack as a three-state memory device are also discussed.

• Geomechanics and Engineering
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• v.28 no.4
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• pp.347-358
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• 2022

The main concern of this article is to discuss the problem of a two-temperature fiber-reinforced micropolar thermoelastic medium with voids under the effect rotation, mechanical force in the context four different theories with memory-dependent derivative (MDD) and variable thermal conductivity. The three-phase-lag model (3PHL), dual-phase-lag model (DPL), Green-Naghdi theory (G-N II, G-N III), coupled theory, and the Lord-Shulman theory (L-S) are employed to solve the present problem. Analytical expressions of the physical quantities are obtained by using Laplace-Fourier transforms technique. Numerical results are shown graphically and the results obtained are analyzed. The most significant points are highlighted.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.

• Journal of the Optical Society of Korea
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• v.14 no.3
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• pp.260-265
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• 2010

This paper proposes a transflective configuration of the dual operating mode liquid crystal display, which has transmissive dynamic and reflective memory parts in its pixel. By employing a wideband structure and optimizing the cell-gap of the liquid crystal layer, the reflective memory part shows a very low reflectance in the dark state, good dispersion properties for the entire visible range, as well as high reflectance in the bright state. The transmissive dynamic part is designed to have the same cell-gap and rubbing direction as those of the reflective part. The driving voltage of the dynamic part and transmittance of the bright state can also be controlled by using compensation film with a positive a-plate, which can compensate the reflective part. Experimental results in the memory part operation demonstrate that the contrast ratio is over 50:1 and the reflectance in the dark state is reduced to 56% on average of that of the conventional dual mode configuration for the entire visible range. The contrast ratio of the dynamic part is 300:1.

• Convergence Security Journal
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• v.15 no.3_1
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• pp.99-105
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• 2015

A typical SRAM-based PUF is used in random number generation and key exchange process. The generated out puts should be preserved, but the values are changed owing to the external environment. This paper presents a new D-PUF logic employing a dual anti-fuse OTP memory to the SRAM-based PUF. The proposed PUF can enhance the reliability of the logic since it can preserve the output values. First, we construct the OTP memory using an anti-fuse. After power up, a SRAM generates the random values owing to the mismatch of cross coupled inverter pair. The generated random values are programed in the proposed anti-fuse ROM. The values that were programed in the ROM at once will not be changed and returned. Thus, the outputs of the proposed D-PUF are not affected by the environment variable such as the operation voltage and temperature variation, etc. Consequently, the reliability of the proposed PUF will be enhanced owing to the proposed dual anti-fuse ROM. Therefore, the proposed D-PUF can be stably operated, in particular, without the powerful ECC in the external environment that are changed.