• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.11
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• pp.31-37
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• 2018

This paper proposes an effective single-image haze-removal algorithm with low complexity by using a dual dark channel prior (DCP) and an adaptive brightness correction technique. The dark channel of a small patch preserves the edge information of the image, but is sensitive to noise and local brightness variations. On the other hand, the dark channel of a large patch is advantageous in estimation of the exact haze value, but halo effects from block effects deteriorate haze-removal performance. In order to solve this problem, the proposed algorithm builds a dual DCP as a combination of dark channels from patches with different sizes, and this meets low-memory and low-complexity requirements, while the conventional method uses a matting technique, which requires a large amount of memory and heavy computations. Moreover, an adaptive brightness correction technique that is applied to the recovered image preserves the objects in the image more clearly. Experimental results for various hazy images demonstrate that the proposed algorithm removes haze effectively, while requiring much fewer computations and less memory than conventional methods.

• The Journal of Korean Physical Therapy
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• v.29 no.6
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• pp.303-306
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• 2017

Purpose: Gait variability is defined as the intrinsic fluctuations which occur during continuous gait cycles. Increased gait variability is closely associated with increased fall risk in older adults. This study investigated the influence of attention-demanding tasks on gait variability in elderly healthy adults. Methods: We recruited 15 healthy elderly adults in this study. All participants performed two cognitive tasks: a subtraction dual-task (SDT) and working memory dual-task (WMDT) during gait plus one normal gait. Using the $LEGSys^+$ system, we measured the coefficient of variation (CV %=$100{\times}$[standard deviation/mean]) for participants' stride time, stride length, and stride velocity. Results: SDT gait showed significant increment of stride time variability compared with usual gait (p<0.05), however, stride length and velocity variability did not difference between SDT gait and usual gait (p>0.05). WMDT gait showed significant increment of stride time and velocity variability compared with usual gait (p<0.05). In addition, stride time variability during WMDT gait also significantly increased compared with SDT gait (p<0.05). Conclusion: We reported that SDT and WMDT gait can induce the increment of the gait variability in elderly adults. We assume that attention demanding task based on working memory has the most influence on the interference between cognitive and gait function. Understanding the changes during dual task gait in older ages would be helpful for physical intervention strategies and improved risk assessment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Journal of Information Display
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• v.10 no.4
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• pp.184-187
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• 2009

A liquid crystal device with switchable dynamic and memory modes was investigated and developed. The proposed device reveals the splay, $\pi$-twist, and bend states via selective switching among them. In the dynamic mode, the device is operated in the bend state, which exhibits a wide viewing-angle and a fast-response-time due to its self-compensated bend structure and flow-accelerated fast response time, respectively. In the memory mode, the permanent memory characteristics in the splay and $\pi$-twist sates are obtained, respectively. The switching mechanisms of the tristate device are also proposed.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.6
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• pp.383-391
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• 2011

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

• BMB Reports
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• v.51 no.8
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• pp.369-370
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• 2018

In previous studies, memory storage was localized to engram cells distributed across the brain. While these studies have provided an individual cellular profile of engram cells, their synaptic connectivity, or whether they follow Hebbian mechanisms, remains uncertain. Therefore, our recent study investigated whether synapses between engram cells exhibit selectively enhanced structural and functional properties following memory formation. This was accomplished using a newly developed technique called "dual-eGRASP". We found that the number and size of spines on CA1 engram cells that receive inputs from CA3 engram cells were larger than at other synapses. We further observed that this enhanced connectivity correlated with induced memory strength. CA3 engram synapses exhibited increased release probability, while CA1 engram synapses produced enhanced postsynaptic responses. CA3 engram to CA1 engram projections showed strong occlusion of long-term potentiation. We demonstrated that the synaptic connectivity of CA3 to CA1 engram cells was strengthened following memory formation. Our results suggest that Hebbian plasticity occurs during memory formation among engram cells at the synapse level.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.606-613
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• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.