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http://dx.doi.org/10.14372/IEMEK.2011.6.6.6

The Efficient Buffer Size in A Dual Flash Memory Structure with Buffer System  

Jung, Bo-Sung (경상대학교 ERI 제어계측공학과)
Lee, Jung-Hoon (경상대학교 ERI 제어계측공학과)
Publication Information
IEMEK Journal of Embedded Systems and Applications / v.6, no.6, 2011 , pp. 383-391 More about this Journal
Abstract
As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.
Keywords
Flash memory; characteristics of instruction and data; dual structure; cache memory;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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