• 정보처리학회논문지A
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• 제8A권4호
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• pp.419-428
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• 2001

집적회로 기술의 발달은 처리기의 속도를 계속적으로 증가시켜 왔다. 처리기 응용분야의 주요한 도전은 공유 메모리 다중 처리기 시스템에서 고성능 처리기들을 효과적으로 사용하고자 하는 것이다. 우리는 상호 연결망 문제가 소규모의 공유 메모리 다중처리기 시스템에서 조차 완전히 해결되었다고 생각하지 않는다. 그 이유는 공유버스의 속도는 새로운 강력한 처리기들의 대역폭 요구를 수용할 수 없기 때문이다. 지난 수년간 점대점 단방향 연결은 매우 가능성 있는 상호 연결망 기술로서 대두되었다. 단일 슬롯링은 점대점 상호 연결망의 가장 간단한 형태이다. 단일 슬롯링 구조의 단점은 링에서 처리기의 수가 증가함에 따라 메모리 접근지연 시간이 선형적으로 증가한다는 것이다. 이런 이유로 우리는 캐쉬 기반의 다중처리기 시스템에서 단일 슬롯링을 대체할 수 있는 이중 슬롯링 구조를 제안한다. 또한 본 논문에서 새로운 스누핑 프로토콜을 사용하는 이중 슬롯링 구조를 분석하고 분석적모델과 모의 실험을 통하여 기존의 단일 슬롯링과 성능을 비교한다.

• 제어로봇시스템학회논문지
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• 제10권2호
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• 전자통신동향분석
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• 제35권3호
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.

• 한국정보전자통신기술학회논문지
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• 제11권6호
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• pp.742-750
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• 2018

본 논문에서는 $0.13{\mu}m$ BCD 공정 기반에서 5V MOS 소자만 사용하여 zero layer FTP 셀이 가능하도록 하기 위해 tunnel oxide 두께를 기존의 $82{\AA}$에서 5V MOS 소자의 gate oxide 두께인 $125{\AA}$을 그대로 사용하였고, 기존의 DNW은 BCD 공정에서 default로 사용하는 HDNW layer를 사용하였다. 그래서 제안된 zero layer FTP 셀은 tunnel oxide와 DNW 마스크의 추가가 필요 없도록 하였다. 그리고 메모리 IP 설계 관점에서는 designer memory 영역과 user memory 영역으로 나누는 dual memory 구조 대신 PMIC 칩의 아날로그 회로의 트리밍에만 사용하는 single memory 구조를 사용하였다. 또한 BGR(Bandgap Reference Voltage) 발생회로의 start-up 회로는 1.8V~5.5V의 전압 영역에서 동작하도록 설계하였다. 한편 64비트 FTP 메모리 IP가 power-on 되면 internal reset 신호에 의해 initial read data를 00H를 유지하도록 설계하였다. $0.13{\mu}m$ Magnachip 반도체 BCD 공정을 이용하여 설계된 64비트 FTP IP의 레이아웃 사이즈는 $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$)이다.

• 한국정보통신학회논문지
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• 제7권3호
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• pp.384-389
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• 2003

새로운 two-step SOVA 복호기 구조가 제안된다. Trace-back단의 survivor memory에 dual-port RAM 개념이 적용되어, 기존 two-step SOVA 방식에 비해서 복호 지연의 현격한 감소가 가능해진다. Path metric 차이의 절대값이 ACS단 내부에서 계산됨으로써, 기존 two-step SOVA 방식에 비해 시스템의 복잡성이 크게 줄어든다. 제안된 SOVA 복호기 구조는 verilog HDL로 기술되어 동작 시뮬레이션을 거쳐 구조의 타당성이 검증되었으며, FPGA로 구현되었다. 구현된 SOVA복호기는 종래의 비터비 복호기에 가까운 데이터 처리율을 보여주었으며, 구현에 사용된 FPGA 소자 자원은 종래의 비터비 복호기의 약 1.5배 정도이다.

• The Journal of Korean Physical Therapy
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• 제35권3호
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• pp.64-70
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• 2023

Purpose: This study investigated the influence of attention-demanding tasks on gait and measured differences in the temporal, spatial and kinematic characteristics between young healthy adults and elderly healthy adults. Methods: We recruited 16 healthy young adults and 15 healthy elderly adults in this study. All participants performed two cognitive tasks: a subtraction dual-task (SDT) and working memory dual-task (WMDT) during gait plus one normal gait. Using the LEGSys+ system, knee and hip-joint kinematic data during stance and swing phase and spatiotemporal parameter data were assessed in this study. Results: In the elderly adult group, attention-demanding tasks with gait showed a significant decrease in hip-joint motion during the stance phase, compared to the normal gait. Step length, stride length and stride velocity of the elderly adult group were significantly decreased in WMDT gait compared to normal gait (p<0.05). In the young adult group, kinematic data did not show any significant difference. However, stride velocity and cadence during SDT and WMDT gaits were significantly decreased compared to those of normal gait (p<0.05). Conclusion: We determined that attention-demanding tasks during gait in elderly adults can induce decreased hip-joint motion during stance phase and decreased gait speed and stride length to maintain balance and prevent risk of falling. We believe that understanding the changes during gait in older ages, particularly during attention-demanding tasks, would be helpful for intervention strategies and improved risk assessment.

• 대한산업공학회지
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• 제10권2호
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• pp.3-16
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• 1984

This study develops a scientific method in pilot selection by analysing a divided attention performance between the successful pilots and the failures in a flight training course. To measure the divided attention performance, Dual Task Method is used in which the primary task is a tracking task while the secondary tasks are, 1. short term memory task, 2. choice reaction task and 3. judgement task. Result shows that the performance of the pilots is significantly better (P < 0.1) than that of the failures in dual performance. In addition, the differences in the divided attention performance between the two groups are increased in proportion to the difficulty of the task and especially in the Short Term Memory, the increment is most dramatic.

• Steel and Composite Structures
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• 제45권4호
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• pp.535-546
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• 2022

The memory response of nonlocal systematical formulation size-dependent coupling of viscoelastic deformation and thermal fields for piezoelectric materials with dual-phase lag heat conduction law is constructed. The method of the matrix exponential, which constitutes the basis of the state-space approach of modern control theory, is applied to the non-dimensional equations. The resulting formulation together with the Laplace transform technique is applied to solve a problem of a semi-infinite piezoelectric rod subjected to a continuous heat flux with constant time rates. The inversion of the Laplace transforms is carried out using a numerical approach. Some comparisons of the impacts of nonlocal parameters and time-delay constants for various forms of kernel functions on thermal spreads and thermo-viscoelastic response are illustrated graphically.

• Educational Technology International
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• 제10권2호
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• pp.145-166
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• 2009

The purpose of this study was to investigate why advance organizers (AO) are effective in promoting comprehension and mental model formation in terms of cognitive load. Two experimental groups: a concept-map AO group and a key-word AO group and one control group were used. This study considered cognitive load in view of Baddeley's working memory model: central executive (CE), phonological loop (PL), and visuo-spatial sketch pad (VSSP). The present experiment directly examined cognitive load using dual task methodology. The results were as follows: central executive (CE) suppression task achievement for the concept map AO group was higher than the key word AO group and control group. Comprehension and mental model construction for the concept map AO group were higher than the other groups. These results indicated that the superiority of concept map AO owing to CE load decrement occurred with comprehension and mental model construction in learning. Thus, the available resources produced by CE load reduction may have been invested for comprehension and mental model construction of learning contents.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.567-570
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• 2005

Most researches on monostable LCD and bistable LCD have separately been carried out. We introduce a novel liquid crystal display mode which can be operated as both memory mode and dynamic mode. The novel LCD mode has not only a long term memory time of memory mode but also a fast response time of dynamic mode. We describe switching characteristics of dual mode. Electro-optical characteristics of memory mode and dynamic mode are unique and show the possibility of device application.