• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.419-428
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• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.384-389
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• 2003

A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.

• The Journal of Korean Physical Therapy
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• v.35 no.3
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• pp.64-70
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• 2023

Purpose: This study investigated the influence of attention-demanding tasks on gait and measured differences in the temporal, spatial and kinematic characteristics between young healthy adults and elderly healthy adults. Methods: We recruited 16 healthy young adults and 15 healthy elderly adults in this study. All participants performed two cognitive tasks: a subtraction dual-task (SDT) and working memory dual-task (WMDT) during gait plus one normal gait. Using the LEGSys+ system, knee and hip-joint kinematic data during stance and swing phase and spatiotemporal parameter data were assessed in this study. Results: In the elderly adult group, attention-demanding tasks with gait showed a significant decrease in hip-joint motion during the stance phase, compared to the normal gait. Step length, stride length and stride velocity of the elderly adult group were significantly decreased in WMDT gait compared to normal gait (p<0.05). In the young adult group, kinematic data did not show any significant difference. However, stride velocity and cadence during SDT and WMDT gaits were significantly decreased compared to those of normal gait (p<0.05). Conclusion: We determined that attention-demanding tasks during gait in elderly adults can induce decreased hip-joint motion during stance phase and decreased gait speed and stride length to maintain balance and prevent risk of falling. We believe that understanding the changes during gait in older ages, particularly during attention-demanding tasks, would be helpful for intervention strategies and improved risk assessment.

• Journal of Korean Institute of Industrial Engineers
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• v.10 no.2
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• pp.3-16
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• 1984

This study develops a scientific method in pilot selection by analysing a divided attention performance between the successful pilots and the failures in a flight training course. To measure the divided attention performance, Dual Task Method is used in which the primary task is a tracking task while the secondary tasks are, 1. short term memory task, 2. choice reaction task and 3. judgement task. Result shows that the performance of the pilots is significantly better (P < 0.1) than that of the failures in dual performance. In addition, the differences in the divided attention performance between the two groups are increased in proportion to the difficulty of the task and especially in the Short Term Memory, the increment is most dramatic.

• Steel and Composite Structures
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• v.45 no.4
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• pp.535-546
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• 2022

The memory response of nonlocal systematical formulation size-dependent coupling of viscoelastic deformation and thermal fields for piezoelectric materials with dual-phase lag heat conduction law is constructed. The method of the matrix exponential, which constitutes the basis of the state-space approach of modern control theory, is applied to the non-dimensional equations. The resulting formulation together with the Laplace transform technique is applied to solve a problem of a semi-infinite piezoelectric rod subjected to a continuous heat flux with constant time rates. The inversion of the Laplace transforms is carried out using a numerical approach. Some comparisons of the impacts of nonlocal parameters and time-delay constants for various forms of kernel functions on thermal spreads and thermo-viscoelastic response are illustrated graphically.

• Educational Technology International
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• v.10 no.2
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• pp.145-166
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• 2009

The purpose of this study was to investigate why advance organizers (AO) are effective in promoting comprehension and mental model formation in terms of cognitive load. Two experimental groups: a concept-map AO group and a key-word AO group and one control group were used. This study considered cognitive load in view of Baddeley's working memory model: central executive (CE), phonological loop (PL), and visuo-spatial sketch pad (VSSP). The present experiment directly examined cognitive load using dual task methodology. The results were as follows: central executive (CE) suppression task achievement for the concept map AO group was higher than the key word AO group and control group. Comprehension and mental model construction for the concept map AO group were higher than the other groups. These results indicated that the superiority of concept map AO owing to CE load decrement occurred with comprehension and mental model construction in learning. Thus, the available resources produced by CE load reduction may have been invested for comprehension and mental model construction of learning contents.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.567-570
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• 2005

Most researches on monostable LCD and bistable LCD have separately been carried out. We introduce a novel liquid crystal display mode which can be operated as both memory mode and dynamic mode. The novel LCD mode has not only a long term memory time of memory mode but also a fast response time of dynamic mode. We describe switching characteristics of dual mode. Electro-optical characteristics of memory mode and dynamic mode are unique and show the possibility of device application.