• ETRI Journal
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• v.30 no.5
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• pp.674-684
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• 2008

This paper proposes a dual addressing scheme (DAS) for IPv6 over IEEE 802.15.4 wireless sensor networks (WSN). DAS combines a global unicast address to cope with association link changes and node mobility, and it links local addresses to lighten the overhead of the system to save energy and resources. This paper describes DAS address formats, address autoconfiguration, and address translation tables in the gateway. A detailed description of DAS is provided through examples. Simulations are performed to demonstrate the performance improvements of the DAS compared with the IPv6-based WSN, which uses the conventional single address.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.12
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• pp.1065-1069
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• 2002

The addressing time should be reduced by modifying cell structure and/or driving method in order to replace the dual scan system by single scan and increase the luminance in large ac plasma display panel(PDP). In this paper, the effects of the addressing time was decreased with decreasing thickness of dielectric layer on the front glass and thickness of white dielectric layer on the rear glass. the decreasing rate were 160ns/10$\mu\textrm{m}$ and 270ns/10$\mu\textrm{m}$, respectively Also in case of decreasing the height of barrier rib, addressing time was decreased at the rate of Sons/10$\mu\textrm{m}$.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1827-1829
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• 2000

To replace the dual scan system by single scan in large ac plasma display(PDP), the addressing time should be reduced by modifying cell structure and driving circuits. Moreover. the luminance of the PDP can be also increased with the decrease in the addressing time. In this paper, various shapes of bus and address electrode have been investigated to reduce the addressing time in ADS driving method. The experimental results show that the addressing time can be reduced more than 30% compared to the conventional type by modifying the electrodes without reducing the luminance of the PDP.

• Journal of Information Display
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• v.2 no.1
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• pp.10-13
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• 2001

The addressing time can be reduced by modifying cell structure and/or driving circuits in order to replace the dual scan system by single scan in large ac plasma display panel(PDP). Moreover, the luminance of the PDP can also be increased by decreasing the addressing time. In this paper, various shapes of bus and address electrodes have been investigated with the aim of reducing the addressing time in ADS driving method. The experimental results show that the addressing time can be reduced by more than 30% compared with the conventional type by modifying the electrodes without reducing the luminance of the PDP.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1824-1826
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• 2000

Up to date, the dual scanning method has been adopted to decrease address-ing period in AC PDP. In this case, addressing period can be reduced, but the driving circuit cost should be increased. In this study, to increase addressing speed we have studied the relationship between addressing speed and cell structure. That is to say, we varied the thickness of dielectric layer on the front glass, the thickness of white back and the height of barrier rib on the rear glass. So, we found that the addressing time was decreased 4% with decreasing 5um thickness of dielectric layer on the front glass and 2um thickness of white back on the rear glass. Also in case of decreasing the height of barrier rib, addressing time was decreased about 4% per 10um.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.247-250
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• 2005

In this paper, new address electrode having separated dual electrodes is suggested to reduce addressing time in ac PDP. It had been found that both the formative and jitter width of the suggested electrode are improved by $10{\sim}20$ % compared with the conventional one on IMID 04'. So we experiment other several kinds of the separated electrodes, and the change in discharge characteristics is analyzed by using a two-dimensional fluid simulation. The key feature of the suggested structure is that the distribution of Xe and Ne ion is controllable during the address periods without significant increases in the capacitive load of the address electrodes.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.734-738
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• 2003

The addressing time should be reduced by modifying cell and/or driving method in order to replace the dual scan system by single scan and increase the luminance in large ac plasma display panel(PDP). In this paper, the relationships between of discharge cell structure and addressing time in ac PDP are investigated. It is found out that the addressing time was decreased with decreasing gap of ITO electrode and thickness of transparence dielectric layer on the front glass. The decrease rates were 4% per $10{\mu}m$ and 4% per $5{\mu}m$, respectively. Also in cases of decreasing height of barrier rip and thickness of white dielectric layer on the rear glass, addressing times were at the rate of 4% per $10{\mu}m$ and 4% per $2{\mu}m$, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.564-567
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• 2004

New address electrode having separated dual electrode is suggested to reduce addressing time in ac PDP. Addressing characteristics of suggested electrode has been investigated in the test panel with high Xe partial pressure. It has been found that both the formative and jitter width of the suggested electrode is improved by 10 -20 % over the wide range of address voltage level compared with the conventional one. The dynamic margin of the panel also greatly improved. The key feature behind this type of structure is that it can extend the controllability of the wall charge distribution during the reset and address discharge without significant increase in capacitive load of address electrode.

• Journal of Communications and Networks
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• v.12 no.5
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• pp.442-448
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• 2010

Cooperative relaying methods have attracted a lot of interest in the past few years. A conventional cooperative relaying scheme has a source, a destination, and a single relay. This cooperative scheme can support one symbol transmission per time slot, and is caned full rate transmission. However, existing fun rate cooperative relay approaches provide asymmetrical gain for different transmitted symbols. In this paper, we propose a cooperative relaying scheme that is assisted with dual relays and provides full transmission rate with the same macro-diversity to each symbol. We also address equalization for the dual relay transmission system in addition to addressing the issues concerning the improvement of system performance in terms of optimal power allocations.

• Journal of KIEE
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• v.11 no.1
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• pp.41-45
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• 2001

The addressing time should be reduced by modifying cell structure and/or driving method in order to replace the dual scan system by single scan and increase the luminance in large ac plasma display panel(PDP). In this paper, the effects of the dielectric layer thickness and the barrier rib height on the addressing time of ac PDP are investigated. It is found out that the addressing time was decreased with decreasing thickness of dielectric layer on the front glass and thickness of white dielectric layer on the rear glass. The decreasing rate were 160ns/10${\mu}{\textrm}{m}$ and 270nsd/10${\mu}{\textrm}{m}$, respectively. Also in case of decreasing the height of barrier rib, addressing time was decreased at the rate of 550ns/10${\mu}m$.