• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.6
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• pp.84-89
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• 2003

In this paper, we real-time implemented to the TMS320C5416 the vocoder of variable bit rate applied the SOLA-B algorithm by Henja to the ITU-T G.729A vocoder of 8kbps transmission rate. This proposed method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. At this time, we bandied that the interval of cross correlation function if skipped every 3 sample for decreasing the computational amount of SOLA-B algorithm. The real-time implemented vocoder of C.729A and SOLA-B algorithm is represented the complexity of maximum that is 10.2MIPS in encoder and 2.8MIPS in decoder of 8kbps transmission rate. Also, it is represented the complexity of maximum that is 18.5MIPS in encoder and 13.1MIPS in decoder of 6kbps, it is 18.5MIPS in encoder and 13.1MIPS in decoder of 4kbps. The used memory is about program ROM 9.7kwords, table ROM 4.5kwords, RAM 5.1 kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, for evaluation of speech quality of the vocoder of real-time implemented variable bit rate, it is estimated the MOS score of 3.69 in 4kbps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of Power Electronics
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• v.11 no.4
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• pp.408-417
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• 2011

The plug-in hybrid electric vehicles (PHEVs) are specialized hybrid electric vehicles that have the potential to obtain enough energy for average daily commuting from batteries. The PHEV battery would be recharged from the power grid at home or at work and would thus allow for a reduction in the overall fuel consumption. This paper proposes an integrated power electronics interface for PHEVs, which consists of a novel Eight-Switch Inverter (ESI) and an interleaved DC/DC converter, in order to reduce the cost, the mass and the size of the power electronics unit (PEU) with high performance at any operating mode. In the proposed configuration, a novel Eight-Switch Inverter (ESI) is able to function as a bidirectional single-phase AC/DC battery charger/ vehicle to grid (V2G) and to transfer electrical energy between the DC-link (connected to the battery) and the electric traction system as DC/AC inverter. In addition, a bidirectional-interleaved DC/DC converter with dual-loop controller is proposed for interfacing the ESI to a low-voltage battery pack in order to minimize the ripple of the battery current and to improve the efficiency of the DC system with lower inductor size. To validate the performance of the proposed configuration, the indirect field-oriented control (IFOC) based on particle swarm optimization (PSO) is proposed to optimize the efficiency of the AC drive system in PHEVs. The maximum efficiency of the motor is obtained by the evaluation of optimal rotor flux at any operating point, where the PSO is applied to evaluate the optimal flux. Moreover, an improved AC/DC controller based Proportional-Resonant Control (PRC) is proposed in order to reduce the THD of the input current in charger/V2G modes. The proposed configuration is analyzed and its performance is validated using simulated results obtained in MATLAB/ SIMULINK. Furthermore, it is experimentally validated with results obtained from the prototypes that have been developed and built in the laboratory based on TMS320F2808 DSP.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5A
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• pp.473-483
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• 2004

In this paper, we numerically investigated the optimum pump light power best compensating for pulse distortion due to both chromatic dispersion and self phase modulation (SPM) as a function of channel input power in 8 channel ${\times}$ 40 Gbps wavelength division multiplexing (WDM systems. Also we investigated the allowable maximum channel input power dependence on modulation format and fiber dispersion coefficient in the various pump light power of OPC. The considered WDM transmission system is based on path-averaged intensity approximation (PAIA) mid-span spectral inversion (MSSI) compensation method, which has highly-nonlinear dispersion shifted fiber (HNL-SDF) as nonlinear medium of optical phase conjugator (OPC) in the mid-way of total transmission line. We confirmed that optimal pump light power of HNL-DSF OPC depend on modulation format, initial channel input power, total transmission length and fiber dispersion. But optimal pump light power of HNL-DSF OPC must be selected to make power conversion ratio to almost unity. And we confirmed that, if we allow a 1 dB eye opening penalty (EOP), the tolerable maximum channel input power is increased by using RZ than NRZ as modulation format when pump light power of HNL-DSF OPC is not optimal value but another values.

• Journal of Life Science
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• v.23 no.4
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• pp.479-486
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• 2013

The DNA-binding protein from starved cells (DPS), originally identified as a DNA binding protein in Escherichia coli, is known to play an important role in DNA protection. The aim of this study was to evaluate the functional roles of DPS in E. coli against various kinds of external stresses by comparing the properties of wild-type E. coli cells and dps knockout mutant E. coli (${\Delta}dps$) cells. Under various stress conditions, we measured the cell growth of the wild-type E. coli and the dps knockout mutant E. coli (${\Delta}dps$) cells using a UV spectrophotometer. The growth rate of the cells was compared to investigate the functional roles of the DPS protein in E. coli. In comparison to the properties of the wild-type E. coli cells, the dps knockout mutant E. coli (${\Delta}dps$) cells showed highly sensitive phenotypes under various stress conditions, such as heat shock, acidic pH, nutrient deficiency, and different concentrations of reactive oxygen species (ROS), suggesting that DPS plays key roles in E. coli in combating diverse external stresses. The DPS DNA-binding protein in E. coli plays crucial roles in bacterial cell growth and in the protection of the cells from environmental stresses by tightly binding and preserving their DNA molecules.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.115-121
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• 2015

In this paper, we proposed an iterative data-flow optimal scheduling algorithm based on genetic algorithm for high-performance multiprocessor. The basic hardware model can be extended to include detailed features of the multiprocessor architecture. This is illustrated by implementing a hardware model that requires routing the data transfers over a communication network with a limited capacity. The scheduling method consists of three layers. In the top layer a genetic algorithm takes care of the optimization. It generates different permutations of operations, that are passed on to the middle layer. The global scheduling makes the main scheduling decisions based on a permutation of operations. Details of the hardware model are not considered in this layer. This is done in the bottom layer by the black-box scheduling. It completes the scheduling of an operation and ensures that the detailed hardware model is obeyed. Both scheduling method can insert cycles in the schedule to ensure that a valid schedule is always found quickly. In order to test the performance of the scheduling method, the results of benchmark of the five filters show that the scheduling method is able to find good quality schedules in reasonable time.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.2
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• pp.138-147
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• 2009

In this paper, improved direct torque control(DTC) system for five-phase squirrel-cage induction motor(IM) is proposed. Due to the additional degrees of freedom, five-phase 1M drives present unique characteristics. Also five-phase motor drives possess many other advantages compared with the traditional three-phase motor drive system, such as reducing an amplitude of torque pulsation and increasing the reliability. The DTC method is advantageous when it is applied to the five-phase IM, because the five-phase inverter provides 32 space vectors in comparison to 8 space voltage vectors into the three-phase inverter. However, five-phase motor has structural drawback of 3rd space-harmonics current component, it is necessary to controlled 3rd harmonic current. So to control 3rd harmonic current and enhance dynamic characteristics of five-phase squirrel-cage IM drive, modified DTC method should be demanded. The characteristics and dynamic performance of traditional five-phase DTC are analyzed and new DTC for five-phase IM is presented. A more precise flux and torque control algorithm for the drives can be suggested and explained For presenting the superior performance of the proposed direct torque control, experimental results are presented using a 32-[bit] fixed point TMS320F2812 digital signal processor with 2.2[kW] induction motor.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.98-106
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• 2001

This paper presents external load disturbance compensation that used to deadbeat load torque observer and regulation of the compensation gain by parameter estimator. As a result, the response of PMSM follows that of the nominal plant. The load torque compensation method is compose of a dead beat observer that is well-known method. However it has disadvantage such as a noise amplification effect. To reduce of the effect, the post-filter, which is implemented by MA process, is proposed. The parameter compensator with RLSM(recursive least square method) parameter estimator is suggested to increase the performance of the load torque observer and main controller. Although RLSM estimator is one of the most effective methods for online parameter identification, it is difficult to obtain unbiased result in this application. It is caused by disturbed dynamic model with external torque. The proposed RLSM estimator is combined with a high performance torque observer to resolve the problems. As a result, the proposed control system becomes a robust and precise system against the load torque and the parameter variation. A stability and usefulness, through the verified computer simulation and experiment, are shown in this paper.