Browse > Article
http://dx.doi.org/10.3745/KIPSTA.2006.13A.5.413

Run-time Memory Optimization Algorithm for the DDMB Architecture  

Cho, Jeong-Hun (경북대학교 전자전기컴퓨터학부)
Paek, Yun-Heung (서울대학교 전기컴퓨터공학부)
Kwon, Soo-Hyun (경북대학교 전자공학과)
Publication Information
The KIPS Transactions:PartA / v.13A, no.5, 2006 , pp. 413-420 More about this Journal
Abstract
Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.
Keywords
Run-time environment; DSP; dual data memory banks; compiler; on-chip memory;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Sudarsanam, A. and Malik, S. 2000. Simultaneous Reference Allocation in Code Generation for Dual Data Memory Bank ASIPs. ACM Transactions on Design Automation of Electronic Systems, Vol.5, No.2, pp.242 - 264, April   DOI   ScienceOn
2 Saghir, M. A. R., Chow, P., and Lee, C. G. 1996. Exploiting Dual Data-Memory Banks in Digital Signal Processors. ACM SIGOPS Operating Systems, pp.234 - 243   DOI
3 Liem, C. 1997. Retargetable Compilers for Embedded Core Processors. Kluwer Academic Publishers
4 Aho, A. V., Sethi, R., and Ullman, J. D. 1986. Compilers-Principles, Techniques, and Tools. Addison-Wesley Publishing Company
5 Leupers, R. and Kotte, D. 2001. Variable partitioning for dual memory bank DSPs. In Proceedings of the IEEE International Conference on Acoustics Speech and Signal Processing. 1121-1124   DOI
6 Lee, C., Potkonjak, M., and Mangione-Smith, W. 1997. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In Proceedings of the 30th Annaul IEEE/ ACM Internation Symposium on Microarchitecture, pp.330 - 335, Nov   DOI
7 Cho, J., Paek, Y., AND Whalley, D. 2004. Fast Memory Bank Assignment for Fixed-Point Digital Processors. and Transactions on Design Automation of Electronic Systems, Vol.9, No.1, pp.52 - 74, Jan   DOI   ScienceOn
8 Motorola Inc. 1999. http//www.motorola-dsp.com. DSP56301 User's Manual