• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.826-830
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• 2013

In this paper, we carried out the investigations of both etch characteristics and mechanisms for the $SnO_2$ thin films in $O_2/BCl_3/Ar$ plasma. The dry etching characteristics of the $SnO_2$ thin films was studied by varying the $O_2/BCl_3/Ar$ gas mixing ratio. We determined the optimized process conditions that were as follows: a RF power of 700 W, a DC-bias voltage of - 150 V, and a process pressure of 2 Pa. The maximum etch rate was 509.9 nm/min in $O_2/BCl_3/Ar$=(3:4:16 sccm) plasma. From XPS analysis, the etch mechanism of the $SnO_2$ thin films in the $O_2/BCl_3/Ar$ plasma can be identified as the ion-assisted chemical reaction while the role of ion bombardment includes the destruction of the metal-oxide bonds as well as the cleaning of the etched surface form the reaction products.

• ETRI Journal
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• v.27 no.3
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.406-406
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• 2010

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.11-16
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• 2002

In this study, the dry etching characteristics of $SrBi_2Ta_2O_9$ (SBT) thin films were investigated by using ICP-RIE (inductively coupled plasma-reactive ion etching). The etching damage and degradation were analyzed with XPS (X-ray photoelectron spectroscopy) and C-V (Capacitance-Voltage) measurement. The etching rate increased with increasing the ICP power and the capacitively coupled plasma (CCP) power. The etch rate of 900$\AA$/min was obtained with 700 W of ICP power and 200 W of CCP power. The main problem of dry etching is the degradation of the ferroelectric material. The damage-free etching characteristics were obtained with the $Ar/C1_2/CHF_3$ gas mixture of 20/14/2 when the ICP power and CCP power were biased at 700 W and 200 W, respectively. The experimental results show that the dry etching process with ICP-RIE is applicable to the fabrication of the single transistor type ferroelectric memory device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.288-295
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• 2009

We report the etch characteristics of GaAs and AlGaAs in the diffusion pump-based capacitively coupled $BCl_3$ plasma. Process variables were chamber pressure ($50{\sim}180$ mTorr), CCP power ($50{\sim}200\;W$) and $BCl_3$ gas flow rate ($2.5{\sim}10$ sccm). Surface profilometry was used for etch rate and surface roughness measurement after etching. Scanning electron microscopy was used to analyze the etched sidewall and surface morphology. Optical emission spectroscopy was used in order to characterize the emission peaks of the $BCl_3$ plasma during etching. We have achieved $0.25{\mu}m$/min of GaAs etch rate with only 5 sccm $BCl_3$ flow rate when the chamber pressure was in the range of 50{\sim}130 mTorr. The etch rates of AlGaAs were a little lower than those of GaAs at the conditions. However, the etch rates of GaAs and AlGaAs decreased significantly when the chamber pressure increased to 180 mTorr. GaAs and AlGaAs were not etched with 50 W CCP power. With $100{\sim}200\;W$ CCP power, etch rates of the materials increased over $0.3{\mu}m$/min. It was found that the etch rates of GaAs and AlGaAs were not always proportional to the increase of CCP power. We also found the interesting result that AlGaAs did not etched at 2.5 sccm $BCl_3$ flow rate at 75 mTorr and 100 W CCP power even though it was etched fast like GaAs with more $BCl_3$ gas flow rates. By contrast, GaAs was etched at ${{\sim}}0.3{\mu}m$/min at the 2.5 sccm $BCl_3$ flow rate condition. A broad molecular peak was noticed in the range of $500{\sim}700\;mm$ wavelength during the $BCl_3$ plasma etching. SEM photos showed that 10 sccm $BCl_3$ plama produced more undercutting on GaAs sidewall than 5 sccm $BCl_3$ plasma.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.9
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• pp.103-109
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• 2007

LCD (Liquid Crystal Display) is widely used electronic product. It needs too many processes such as PECVD (Plasma Enhanced Vapor Deposition), Sputtering, Photo-lithography, Dry etch. Each process is important but inspection process is more important because most companies emphasis on the six sigma. Recently, LCD inspection system is composed with inlet, inspector, outlet air pads. LCD is inspected on air pad which is shooting air from air hole. This paper studies on pad design of air bearing for LCD inspection to minimize LCD fluctuation. This design is able to reduce fluctuation and then satisfies CCD inspectional range. Also inspection pad needs to adequate stable area.

• Journal of the Korean Ceramic Society
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• v.46 no.1
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

• Journal of the Korean Vacuum Society
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• v.5 no.2
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• pp.169-174
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• 1996

The applications of the high density plasma sources to the etching in semiconductor fabrication process are actively studied because of the more strict requirement from the dry etching process due to shrinking down of the critical dimension. But in the oxide etching with the high density plasma sources, abundant fluorine atoms released from the flurocarbon feed gas make it difficult to get the highly selective $SiO_2/Si$ etching. In this study, to improve the $SiO_2/Si$ etch selectivity through the control of the radical loss channels, we propose the wall heating , one of methods of controlling loss mechanisms. With appearance mass spectroscopy(AMS) and actinometric optical emission spectroscopy(OES), the increase of both radicals impinging on the substrate and existing in bulk plasma, and the decrease of the fluorine atom with wall temperature are observed. As a result, a 40% improvement of the selectivity was achieved for the carbon rich feed gas.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.519-524
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• 2005

A numerical process to simulate SiO2 dry etching with inductively coupled C2F6 plasmas has been constructed using a commercial CFD code as a first step to design a run-to-run control system. The simulator was tuned to reasonably predict the reactive ion etching behavior and used to investigate the effects of plasma operating variables on the etch rate and uniformity. The relationship between the operating variables and the etching characteristics was mathematically modeled through linear regression for future run-to-run control system design.