• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1011-1014
• /
• 2003

We proposed a new two-stage operational amplifier that increases the slew rate by adding some simple circuitry to the conventional structure. The proposed circuit is simulated by HSPICE and the slew rate of the proposed circuit is improved more than 10 times than that of conventional one in slewing state without considerable increments in area and power consumption.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2009.10a
• /
• pp.717-718
• /
• 2009

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1578-1581
• /
• 2009

This work describes a power and area efficient switched-capacitor cyclic DAC for mobile display drivers. The proposed DAC can be simply implemented with one opamp two capacitors and several switches. Furthermore, the op-amp input referred offset is attenuated at the DAC output without additional offset cancellation circuitry. The operation of the cyclic DAC is verified through circuit level simulations.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.850-853
• /
• 2005

This paper presents issues of display hardware architecture, relating to memory, display driver IC architecture, and chip-to-chip interface. To achieve a low power and low cost mobile phone, not only the display architecture must be carefully selected, but also the driver-ICs optimized to accommodate the different modes of operation found in typical handheld devices. The technique of forming a photo sensor in each pixel using TFT and display module architecture are developed to add multi functions in display such as fingerprint recognition, image scanning, and integrated touch screen. Detailed architectures of IC partitioning, high-speed serial interface, D/A converter, and multi functions such as fingerprint recognition and image scanning using photo sensors are important to a power optimized system.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.3
• /
• pp.13-18
• /
• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.470-473
• /
• 2009

We have developed a novel driving method, Six times Rate Driving(SRD) for the purpose of making cost competitive TFT-LCD. By applying SRD method to an a-Si TFT-LCD, the driving rate was increased six times as it was named but the number of data lines and so its D-Ics were reduced to one sixth of the conventional one which resulted in the cost saving of that much. We also newly designed the gate driver in order to avoid any expansion of the bezel width caused by applying SRD. Our newly developed driving technology, SRD was successfully applied to 7.0-inch WSVGA (1024 ${\times}$ 600) TFT-LCD which can be driven with only one data D-IC and here introduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.3
• /
• pp.213-216
• /
• 2008

The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in $I_D-V_G$ curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.2116-2118
• /
• 2000

In the technique of Q-switching, very fast electronically controlled optical shutters can be made by using the electro-optic effect in crystals or liquids. The driver for the Pockels cell must be a high-speed, high-voltage switch which also must deliver a sizeable current. Common switching techniques include the use of vacuum tubes, cold cathode tubes, thyratrons, SCRs, and avalanche transistors. Semiconductor devices such as SCRs, avalanche transistors, and MOSFETs have been successfully employed to drive Pockels cell Q-switch. In this study, a simple driver for the Pockels cell Q-switch was developed by using SCRs, pulse transformer and TTL ICs. The Pockels cell Q-switch which was operated by this driver was employed in pulsed Nd:YAG laser system to investigate the operating characteristics of this Q-switch. And we have investigated the output characteristics of this Q-switch as a function of the Q-switch delay time to Xe flashlamp current on.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.8 no.2
• /
• pp.107-115
• /
• 2015

In this paper, a small-area 32-bit differential paired eFuse OTP memory for power ICs is designed. In case of smaller number of rows than that of columns for the OTP memory cell array, a scheme for the cell array reducing the number of SL driver circuits requiring their larger layout areas by routing the SL (source line) lines supplying programming currents for eFuse links in the row direction instead of the column direction as well as a core circuit is proposed. In addition, to solve a failure of being blown for non-blown eFuse links by the electro-migration phenomenon, a regulated voltage of V2V ($=2V{\pm}0.2V$) is used to a RWL (read word line) driver circuit and a BL (bit line) pull-up driver circuit. The layout size of the designed 32-bit eFuse OTP memory is $228.525{\mu}m{\times}105.435{\mu}m$, which is confirmed to be 20.7% smaller than that of the counterpart using the conventional cell array routing, namely $197.485{\mu}m{\times}153.715{\mu}m$.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.463-464
• /
• 2008

As the demands of LCD and PDP TV are increasing, the high performance HVICs(High Voltage Gate Driver ICs) technology is becoming more necessary. In this paper, we designed the HVIC that has enhanced noise immunity and high driving capability. It can operate at 500KHz switching frequency and permit 600V input voltage. High-side level shifter is designed with noise protection circuit and schmitt trigger. Therefore it has very high dv/dt immunity, the maximum being 50V/ns. The HVIC was designed using $1{\mu}m$ BCD 650V process and verified by Spectre and PSpice of Cadence inc. simulation.